Nameable

core

BitVector Bits Bool SInt UInt

core

core

ExtractBitsVectorFloating RangedAssignmentFloating

SafeStack

SpinalTagReady

AssertNode BaseType BinaryOperator BitAssignmentFixed BitAssignmentFloating Cast ConstantOperator ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating Literal MemReadAsync MemReadSync MemReadWrite_readPart MemReadWrite_writePart MemWrite MultipleAssignmentNode Multiplexer Node NodeWithVariableInputsCount NodeWithoutInputs RangedAssignmentFixed RangedAssignmentFloating Reg Resize SyncNode UnaryOperator WhenNode

MemBlackboxingPolicy blackboxAll blackboxAllWhatsYouCan blackboxOnlyIfRequested blackboxRequestedAndUninferable

Vec

WidthInfer

SpinalConfig

CastBitsToEnum CastBitsToSInt CastBitsToUInt CastBoolToBits CastEnumToBits CastEnumToEnum CastSIntToBits CastSIntToUInt CastUIntToBits CastUIntToSInt ExtractBitsVectorFixedFromBits ExtractBitsVectorFixedFromSInt ExtractBitsVectorFixedFromUInt ExtractBitsVectorFloatingFromBits ExtractBitsVectorFloatingFromSInt ExtractBitsVectorFloatingFromUInt ExtractBoolFixedFromBits ExtractBoolFixedFromSInt ExtractBoolFixedFromUInt ExtractBoolFloatingFromBits ExtractBoolFloatingFromSInt ExtractBoolFloatingFromUInt Modifier MultiplexerBits MultiplexerBool MultiplexerEnum MultiplexerSInt MultiplexerUInt AllByBool And Cat Equal Not NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Xor And Equal Not NotEqual Or Xor Equal NotEqual Add AllByBool And Div Equal Minus Mod Mul Not NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Smaller SmallerOrEqual Sub Xor Add AllByBool And Div Equal Mod Mul Not NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Smaller SmallerOrEqual Sub Xor ResizeBits ResizeSInt ResizeUInt

PhaseVhdl

PhaseVhdl

PhaseVerilog PhaseVhdl

PhaseVerilog

PhaseVerilog

PhaseVhdl

PhaseVerilog

PhaseVhdl

PhaseVerilog PhaseVhdl

PhaseVerilog PhaseVhdl

PhaseVerilog

PhaseVerilog

PhaseVerilog

PhaseVerilog PhaseVhdl

BitVector

Process

WrappedStuff

WhenContext

VhdlTestBenchBackend core

PhaseVerilog PhaseVhdl

core

VhdlTestBenchBackend

GlobalData