spinal.core.VhdlVerilogBase

Process

Related Doc: package VhdlVerilogBase

class Process extends AnyRef

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Instance Constructors

  1. new Process(order: Int)

Value Members

  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. final def asInstanceOf[T0]: T0

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  5. def clone(): AnyRef

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    protected[java.lang]
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    @throws( ... )

  6. final def eq(arg0: AnyRef): Boolean

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  7. def equals(arg0: Any): Boolean

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  8. def finalize(): Unit

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    protected[java.lang]
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    @throws( classOf[java.lang.Throwable] )

  9. def genSensitivity: Unit

  10. final def getClass(): Class[_]

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  11. var hasMultipleAssignment: Boolean

  12. def hashCode(): Int

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  13. final def isInstanceOf[T0]: Boolean

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  14. final def ne(arg0: AnyRef): Boolean

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  15. def needProcessDef: Boolean

  16. val nodes: ArrayBuffer[Node]

  17. final def notify(): Unit

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  18. final def notifyAll(): Unit

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  19. val order: Int

  20. var sensitivity: Set[Node]

  21. final def synchronized[T0](arg0: ⇒ T0): T0

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  22. def toString(): String

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  23. final def wait(): Unit

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    @throws( ... )

  24. final def wait(arg0: Long, arg1: Int): Unit

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    @throws( ... )

  25. final def wait(arg0: Long): Unit

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  26. val whens: ArrayBuffer[ConditionalContext]

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