spinal.core

SpinalConfig

Related Docs: object SpinalConfig | package core

case class SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, forceMemToBlackboxTranslation: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", dumpWave: DumpWaveConfig = null) extends Product with Serializable

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Instance Constructors

  1. new SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, forceMemToBlackboxTranslation: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", dumpWave: DumpWaveConfig = null)

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  4. def apply[T <: Component](gen: ⇒ T): SpinalReport[T]

  5. def applyToGlobalData(globalData: GlobalData): Unit

  6. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  7. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
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    Annotations
    @throws( ... )

  8. val debug: Boolean

  9. val defaultClockDomainFrequency: IClockDomainFrequency

  10. val defaultConfigForClockDomains: ClockDomainConfig

  11. def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig

  12. val dumpWave: DumpWaveConfig

  13. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  14. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
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    Annotations
    @throws( classOf[java.lang.Throwable] )

  15. val forceMemToBlackboxTranslation: Boolean

  16. def generate[T <: Component](gen: ⇒ T): SpinalReport[T]

  17. def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]

  18. def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]

  19. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  20. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  21. val mode: SpinalMode

  22. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  23. final def notify(): Unit

    Definition Classes
    AnyRef

  24. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  25. val onlyStdLogicVectorAtTopLevelIo: Boolean

  26. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  27. val targetDirectory: String

  28. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  29. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
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    @throws( ... )

  30. final def wait(arg0: Long): Unit

    Definition Classes
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    @throws( ... )

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Inherited from Product

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