RISING
core
Ram_1w_1ra
core
Ram_1w_1rs
core
Ram_1wors
core
Ram_1wrs
core
Ram_2c_1w_1rs
core
Ram_2wrs
core
RangePimper
core
RangedAssignmentFixed
internals
RangedAssignmentFloating
internals
ReadUnderWritePolicy
core
Ref
core
RefOwnerType
Component OwnableRef
Reg
core
RegInit
core
RegNext
core
RegNextWhen
core
ResetArea
core
ResetKind
core
ResetTag
core
Resize
internals
ResizeBits
internals
ResizeSInt
internals
ResizeUInt
internals
ramBlock
core
randBoot
Data Mem
randomBoot
core
range
BitVector Vec
raw
XFix
rawFactory
SFix UFix XFix
read
Vec
readAsync
Mem
readAsyncImpl
Mem
readClockEnableWire
ClockDomain
readClockWire
ClockDomain
readEnable
MemReadSync
readFirst
core
readResetWire
ClockDomain
readSoftResetWire
ClockDomain
readSync
Mem
readSyncCC
Mem
readSyncImpl
Mem
readSyncMixedWidth
Mem
readUnderWrite
MemReadAsync MemReadSync
readUnderWriteString
ReadUnderWritePolicy dontCare readFirst writeFirst
readWriteSync
Mem MemTopology
readWriteSyncImpl
Mem
readWriteSyncMixedWidth
Mem
readsAsync
MemTopology
readsSync
MemTopology
refImpl
ComponentEmiterVerilog ComponentEmiterVhdl
refOwner
OwnableRef
referenceSetAdd
ComponentEmiterVerilog ComponentEmiterVhdl
referenceSetPause
ComponentEmiterVerilog ComponentEmiterVhdl
referenceSetResume
ComponentEmiterVerilog ComponentEmiterVhdl
referenceSetSorted
ComponentEmiterVerilog ComponentEmiterVhdl
referenceSetStart
ComponentEmiterVerilog ComponentEmiterVhdl
referenceSetStop
ComponentEmiterVerilog ComponentEmiterVhdl
referencesOverrides
ComponentEmiter
reflect
Misc
reflectExclusion
Misc
reflectNames
Area
reflectiveCalls
core
registerFile
core
remapDrivingExpressions
AssignmentStatement BitAssignmentFixed BitAssignmentFloating ExpressionContainer RangedAssignmentFixed RangedAssignmentFloating
remapElementsExpressions
SwitchStatement
remapExpressions
MemReadAsync MemReadSync MemReadWrite MemWrite AnalogDriver AssertStatement AssignmentStatement BinaryMultiplexer BinaryOperator BitAssignmentFixed BitAssignmentFloating BitVectorBitAccessFixed BitVectorBitAccessFloating BitVectorRangedAccessFixed BitVectorRangedAccessFloating Cast ConstantOperator DeclarationStatement ExpressionContainer Literal Multiplexer RangedAssignmentFixed RangedAssignmentFloating Resize SwitchStatement SwitchStatementKeyBool UnaryOperator WhenStatement
remove
AssignedBits
removeAssignments
BaseType Data
removeStatement
BaseType Statement StatementDoubleLinkedContainerElement
removeStatementFromScope
Statement
removeTag
SpinalTagReady
removeTags
SpinalTagReady
replaceStdLogicByStdULogic
BlackBox
report
core
reservedKeyWords
PhaseContext
reset
ClockDomain GlobalData SafeStack
resetActiveLevel
ClockDomainConfig
resetKind
ClockDomainConfig
resetSim
ClockDomainPimper
resize
BitVector Bits SInt UInt InputNormalize
resizeFactory
Bits Add And Or Sub Xor And Or Xor Add And Or Sub Xor Add And Or Sub Xor
resizeFunction
ComponentEmiterVhdl
resizeLeft
Bits
resized
Data
resizedOrUnfixedLit
InputNormalize
resolution
SFix UFix XFix
result
ComponentEmiterVerilog ComponentEmiterVhdl
rework
Component
right
BinaryOperator
rise
Bool BoolEdges
risingEdge
ClockDomainPimper
rootScopeStatement
BaseType AssignmentStatement Statement
rotateLeft
BitVector Bits SInt UInt
rotateRight
BitVector Bits SInt UInt
roundUp
core
rtl
SpinalVerilatorBackendConfig
rtlSourcesPaths
SpinalReport