spinal.core.internals

ComponentEmiterVerilog

Related Doc: package internals

class ComponentEmiterVerilog extends ComponentEmiter

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ComponentEmiter, AnyRef, Any
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  2. ComponentEmiter
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Visibility
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Instance Constructors

  1. new ComponentEmiterVerilog(c: Component, verilogBase: VerilogBase, algoIdIncrementalBase: Int, mergeAsyncProcess: Boolean, asyncResetCombSensitivity: Boolean, anonymSignalPrefix: String, nativeRom: Boolean, nativeRomFilePrefix: String, emitedComponentRef: ConcurrentHashMap[Component, Component], emitedRtlSourcesPath: LinkedHashSet[String])

Type Members

  1. class AsyncProcess extends AnyRef

    Definition Classes
    ComponentEmiter

  2. class SyncGroup extends AnyRef

    Definition Classes
    ComponentEmiter

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  4. val _referenceSet: LinkedHashSet[String]

  5. var _referenceSetEnabled: Boolean

  6. def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String

  7. def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String

  8. def accessBoolFixed(e: BitVectorBitAccessFixed): String

  9. def accessBoolFloating(e: BitVectorBitAccessFloating): String

  10. val algoIdIncrementalBase: Int

    Definition Classes
    ComponentEmiterVerilog → ComponentEmiter

  11. var algoIdIncrementalOffset: Int

    Definition Classes
    ComponentEmiter

  12. def allocateAlgoIncrementale(): Int

    Definition Classes
    ComponentEmiter

  13. val analogs: ArrayBuffer[BaseType]

    Definition Classes
    ComponentEmiter

  14. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  15. def boolLiteralImpl(e: BoolLiteral): String

  16. val c: Component

  17. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  18. def component: Component

    Definition Classes
    ComponentEmiterVerilog → ComponentEmiter

  19. def cutLongExpressions(): Unit

    Definition Classes
    ComponentEmiter

  20. val declarations: StringBuilder

  21. def dispatchExpression(e: Expression): String

  22. def elaborate(): Unit

    Definition Classes
    ComponentEmiter

  23. def emitAnalogs(): Unit

  24. def emitArchitecture(): Unit

  25. def emitAssignedExpression(that: Expression): String

  26. def emitAsyncronous(process: AsyncProcess): Unit

  27. def emitAsyncronousAsAsign(process: AsyncProcess): Boolean

  28. def emitBaseTypeSignal(baseType: BaseType, name: String): String

  29. def emitBaseTypeWrap(baseType: BaseType, name: String): String

  30. def emitBitVectorLiteral(e: BitVectorLiteral): String

  31. def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit

  32. def emitEntity(): Unit

  33. def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String

  34. def emitEnumPoison(e: EnumPoison): String

  35. def emitExpression(that: Expression): String

  36. def emitExpressionNoWrappeForFirstOne(that: Expression): String

  37. def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int

  38. def emitMem(mem: Mem[_]): Unit

  39. def emitMems(mems: ArrayBuffer[Mem[_]]): Unit

  40. def emitMuxes(): Unit

  41. def emitReference(that: DeclarationStatement, sensitive: Boolean): String

  42. def emitReferenceNoOverrides(that: DeclarationStatement): String

  43. def emitSignals(): Unit

  44. def emitSubComponents(openSubIo: HashSet[BaseType]): Unit

  45. def emitSyncronous(component: Component, group: SyncGroup): Unit

  46. def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String

  47. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  48. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  49. val expressionToWrap: LinkedHashSet[Expression]

    Definition Classes
    ComponentEmiter

  50. def fillExpressionToWrap(): Unit

  51. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  52. def getBaseTypeSignalInitialisation(signal: BaseType): String

  53. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  54. def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

    Definition Classes
    ComponentEmiter

  55. def getTrace(): ComponentEmiterTrace

  56. def hashCode(): Int

    Definition Classes
    AnyRef → Any

  57. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  58. def isSubComponentInputBinded(data: BaseType): BaseType

    Definition Classes
    ComponentEmiter

  59. val logics: StringBuilder

  60. var memBitsMaskKind: MemBitsMaskKind

  61. val mems: ArrayBuffer[Mem[_]]

    Definition Classes
    ComponentEmiter

  62. val mergeAsyncProcess: Boolean

    Definition Classes
    ComponentEmiterVerilog → ComponentEmiter

  63. val multiplexersPerSelect: LinkedHashMap[(Expression with WidthProvider, Int), ArrayBuffer[Multiplexer]]

    Definition Classes
    ComponentEmiter

  64. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  65. final def notify(): Unit

    Definition Classes
    AnyRef

  66. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  67. val openSubIo: HashSet[BaseType]

    Definition Classes
    ComponentEmiter

  68. def operatorImplAsBinaryOperator(verilog: String)(e: BinaryOperator): String

  69. def operatorImplAsBinaryOperatorLeftSigned(vhd: String)(op: BinaryOperator): String

  70. def operatorImplAsBinaryOperatorSigned(vhd: String)(op: BinaryOperator): String

  71. def operatorImplAsCat(e: Cat): String

  72. def operatorImplAsEnumToEnum(e: CastEnumToEnum): String

  73. def operatorImplAsMux(e: BinaryMultiplexer): String

  74. def operatorImplAsNoTransformation(func: Cast): String

  75. def operatorImplAsUnaryOperator(verilog: String)(e: UnaryOperator): String

  76. def operatorImplResize(func: Resize): String

  77. def operatorImplResizeSigned(func: Resize): String

  78. val outputsToBufferize: LinkedHashSet[BaseType]

    Definition Classes
    ComponentEmiter

  79. val portMaps: ArrayBuffer[String]

  80. val processes: LinkedHashSet[AsyncProcess]

    Definition Classes
    ComponentEmiter

  81. def refImpl(e: BaseType): String

  82. def referenceSetAdd(str: String): Unit

  83. def referenceSetPause(): Unit

  84. def referenceSetResume(): Unit

  85. def referenceSetSorted(): LinkedHashSet[String]

  86. def referenceSetStart(): Unit

  87. def referenceSetStop(): Unit

  88. val referencesOverrides: HashMap[Nameable, Any]

    Definition Classes
    ComponentEmiter

  89. def result: String

  90. def shiftLeftByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String

  91. def shiftLeftByIntImpl(e: ShiftLeftByInt): String

  92. def shiftLeftByUIntImpl(e: ShiftLeftByUInt): String

  93. def shiftLeftByUIntImplSigned(e: ShiftLeftByUInt): String

  94. def shiftRightByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String

  95. def shiftRightByIntImpl(e: ShiftRightByInt): String

  96. def shiftRightSignedByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String

  97. val subComponentInputToNotBufferize: HashSet[Any]

    Definition Classes
    ComponentEmiter

  98. val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean), SyncGroup]

    Definition Classes
    ComponentEmiter

  99. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  100. def toString(): String

    Definition Classes
    AnyRef → Any

  101. var verilogIndexGenerated: Boolean

  102. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  103. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  104. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  105. def wrapSubInput(io: BaseType): Unit

    Definition Classes
    ComponentEmiterVerilog → ComponentEmiter

  106. val wrappedExpressionToName: HashMap[Expression, String]

    Definition Classes
    ComponentEmiter

Inherited from ComponentEmiter

Inherited from AnyRef

Inherited from Any

Ungrouped