ComponentEmitterVerilog

Instance Constructors

new ComponentEmitterVerilog(c: Component, systemVerilog: Boolean, verilogBase: VerilogBase, algoIdIncrementalBase: Int, mergeAsyncProcess: Boolean, asyncResetCombSensitivity: Boolean, anonymSignalPrefix: String, nativeRom: Boolean, nativeRomFilePrefix: String, emitedComponentRef: ConcurrentHashMap[Component, Component], emitedRtlSourcesPath: LinkedHashSet[String], pc: PhaseContext, spinalConfig: SpinalConfig, romCache: HashMap[String, String])

Type Members

class AsyncProcess extends AnyRef

Definition Classes
ComponentEmitter
class SyncGroup extends AnyRef

Definition Classes
ComponentEmitter

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
val _referenceSet: LinkedHashSet[String]
var _referenceSetEnabled: Boolean
def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String
def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String
def accessBoolFixed(e: BitVectorBitAccessFixed): String
def accessBoolFloating(e: BitVectorBitAccessFloating): String
val algoIdIncrementalBase: Int

Definition Classes
ComponentEmitterVerilog → ComponentEmitter
var algoIdIncrementalOffset: Int

Definition Classes
ComponentEmitter
def allocateAlgoIncrementale(): Int

Definition Classes
ComponentEmitter
val analogs: ArrayBuffer[BaseType]

Definition Classes
ComponentEmitter
final def asInstanceOf[T0]: T0

Definition Classes
Any
val beginModule: StringBuilder
def boolLiteralImpl(e: BoolLiteral): String
val c: Component
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@IntrinsicCandidate() @throws( ... )
def commentTagsToString(host: SpinalTagReady, comment: String): String

Definition Classes
ComponentEmitter
def component: Component

Definition Classes
ComponentEmitterVerilog → ComponentEmitter
val createInterfaceWrap: LinkedHashMap[Data, String]

Definition Classes
ComponentEmitter
def cutLongExpressions(): Unit

Definition Classes
ComponentEmitter
val declarations: StringBuilder
val declaredInterface: HashSet[Interface]
val definitionAttributes: StringBuilder
def dispatchExpression(e: Expression): String
def elaborate(): Unit

Definition Classes
ComponentEmitter
def emitAnalogs(): Unit
def emitArchitecture(): Unit
def emitAssignedExpression(that: Expression): String
def emitAsynchronous(process: AsyncProcess): Unit
def emitAsynchronousAsAsign(process: AsyncProcess): Boolean
def emitBaseTypeSignal(baseType: BaseType, name: String): String
def emitBaseTypeWrap(baseType: BaseType, name: String): String
def emitBeginEndModule(): Unit
def emitBitVectorLiteral(e: BitVectorLiteral): String
def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit
def emitEntity(): Unit
def emitEnumDebugLogic(): Unit
def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String
def emitEnumParams(): Unit
def emitEnumPoison(e: EnumPoison): String
def emitExpression(that: Expression): String
def emitExpressionNoWrappeForFirstOne(that: Expression): String
def emitInitials(): Unit
def emitInterfaceSignal(data: Interface, name: String): String
def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int
def emitLocation(that: AssignmentStatement): String
def emitMaskedLiteral(e: MaskedLiteral): String
def emitMem(mem: Mem[_]): Unit
def emitMems(mems: ArrayBuffer[Mem[_]]): Unit
def emitMuxes(): Unit
def emitReference(that: DeclarationStatement, sensitive: Boolean): String
def emitReferenceNoOverrides(that: DeclarationStatement): String
def emitSignals(): Unit
def emitSubComponents(openSubIo: HashSet[BaseType]): Unit
def emitSynchronous(component: Component, group: SyncGroup): Unit
val endModule: StringBuilder
val enumDebugStringList: ArrayBuffer[(SpinalEnumCraft[_ <: SpinalEnum], String, Int)]
def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
val expressionToWrap: LinkedHashSet[Expression]

Definition Classes
ComponentEmitter
def fillExpressionToWrap(): Unit
def getBaseTypeSignalInitBoot(signal: BaseType): String
def getBaseTypeSignalRandBoot(signal: BaseType): String
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
Annotations
@IntrinsicCandidate()
def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

Definition Classes
ComponentEmitter
def getTrace(): ComponentEmitterTrace
def hashCode(): Int

Definition Classes
AnyRef → Any
Annotations
@IntrinsicCandidate()
def idToBits[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String
val initials: ArrayBuffer[LeafStatement]

Definition Classes
ComponentEmitter
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def isSubComponentInputBinded(data: BaseType): Expression

Definition Classes
ComponentEmitter
val localEnums: LinkedHashSet[(SpinalEnum, SpinalEnumEncoding)]
val localparams: StringBuilder
val logics: StringBuilder
var memBitsMaskKind: MemBitsMaskKind
val mems: ArrayBuffer[Mem[_]]

Definition Classes
ComponentEmitter
val mergeAsyncProcess: Boolean

Definition Classes
ComponentEmitterVerilog → ComponentEmitter
val multiplexersPerSelect: LinkedHashMap[(Expression with WidthProvider, Int), ArrayBuffer[Multiplexer]]

Definition Classes
ComponentEmitter
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
Annotations
@IntrinsicCandidate()
final def notifyAll(): Unit

Definition Classes
AnyRef
Annotations
@IntrinsicCandidate()
val openSubIo: HashSet[BaseType]

Definition Classes
ComponentEmitter
def operatorImplAsBinaryOperator(verilog: String)(e: BinaryOperator): String
def operatorImplAsBinaryOperatorLeftSigned(vhd: String)(op: BinaryOperator): String
def operatorImplAsBinaryOperatorSigned(vhd: String)(op: BinaryOperator): String
def operatorImplAsCat(e: Cat): String
def operatorImplAsEnumToEnum(e: CastEnumToEnum): String
def operatorImplAsMux(e: BinaryMultiplexer): String
def operatorImplAsNoTransformation(func: Cast): String
def operatorImplAsUnaryOperator(verilog: String)(e: UnaryOperator): String
def operatorImplResize(func: Resize): String
def operatorImplResizeSigned(func: Resize): String
def outSigCanInline(sig: BaseType): Boolean
val outputNoNeedWrap: LinkedHashSet[Expression]
val outputSignalNoUse: LinkedHashSet[BaseType]
val outputWrap: LinkedHashMap[Expression, String]
val outputsToBufferize: LinkedHashSet[BaseType]

Definition Classes
ComponentEmitter
val portMaps: ArrayBuffer[String]
val processes: LinkedHashSet[AsyncProcess]

Definition Classes
ComponentEmitter
val randBoots: ArrayBuffer[BaseType]
def readedOutputWrapEnable: Boolean

Definition Classes
ComponentEmitter
def refImpl(e: BaseType): String
def referenceSetAdd(str: String): Unit
def referenceSetPause(): Unit
def referenceSetResume(): Unit
def referenceSetSorted(): LinkedHashSet[String]
def referenceSetStart(): Unit
def referenceSetStop(): Unit
val referencesOverrides: HashMap[Nameable, Any]

Definition Classes
ComponentEmitter
def result: String
def shiftLeftByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String
def shiftLeftByIntImpl(e: ShiftLeftByInt): String
def shiftLeftByUIntImpl(e: ShiftLeftByUInt): String
def shiftLeftByUIntImplSigned(e: ShiftLeftByUInt): String
def shiftRightByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
def shiftRightByIntImpl(e: ShiftRightByInt): String
def shiftRightSignedByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
def signalNoUse(sig: BaseType): Boolean
val spinalConfig: SpinalConfig

Definition Classes
ComponentEmitterVerilog → ComponentEmitter
val subComponentInputToNotBufferize: HashSet[Any]

Definition Classes
ComponentEmitter
val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean), SyncGroup]

Definition Classes
ComponentEmitter
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
var verilogIndexGenerated: Boolean
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def wrapSubInput(io: BaseType): Unit

Definition Classes
ComponentEmitterVerilog → ComponentEmitter
val wrappedExpressionToName: HashMap[Expression, String]

Definition Classes
ComponentEmitter

Deprecated Value Members

def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@Deprecated @deprecated @throws( classOf[java.lang.Throwable] )
Deprecated
(Since version ) see corresponding Javadoc for more information.

Related Doc: package internals

class ComponentEmitterVerilog extends ComponentEmitter

Instance Constructors

Type Members

class AsyncProcess extends AnyRef

class SyncGroup extends AnyRef

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

val _referenceSet: LinkedHashSet[String]

var _referenceSetEnabled: Boolean

def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String

def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String

def accessBoolFixed(e: BitVectorBitAccessFixed): String

def accessBoolFloating(e: BitVectorBitAccessFloating): String

val algoIdIncrementalBase: Int

var algoIdIncrementalOffset: Int

def allocateAlgoIncrementale(): Int

val analogs: ArrayBuffer[BaseType]

final def asInstanceOf[T0]: T0

val beginModule: StringBuilder

def boolLiteralImpl(e: BoolLiteral): String

val c: Component

def clone(): AnyRef

def commentTagsToString(host: SpinalTagReady, comment: String): String

def component: Component

val createInterfaceWrap: LinkedHashMap[Data, String]

def cutLongExpressions(): Unit

val declarations: StringBuilder

val declaredInterface: HashSet[Interface]

val definitionAttributes: StringBuilder

def dispatchExpression(e: Expression): String

def elaborate(): Unit

def emitAnalogs(): Unit

def emitArchitecture(): Unit

def emitAssignedExpression(that: Expression): String

def emitAsynchronous(process: AsyncProcess): Unit

def emitAsynchronousAsAsign(process: AsyncProcess): Boolean

def emitBaseTypeSignal(baseType: BaseType, name: String): String

def emitBaseTypeWrap(baseType: BaseType, name: String): String

def emitBeginEndModule(): Unit

def emitBitVectorLiteral(e: BitVectorLiteral): String

def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit

def emitEntity(): Unit

def emitEnumDebugLogic(): Unit

def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String

def emitEnumParams(): Unit

def emitEnumPoison(e: EnumPoison): String

def emitExpression(that: Expression): String

def emitExpressionNoWrappeForFirstOne(that: Expression): String

def emitInitials(): Unit

def emitInterfaceSignal(data: Interface, name: String): String

def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int

def emitLocation(that: AssignmentStatement): String

def emitMaskedLiteral(e: MaskedLiteral): String

def emitMem(mem: Mem[_]): Unit

def emitMems(mems: ArrayBuffer[Mem[_]]): Unit

def emitMuxes(): Unit

def emitReference(that: DeclarationStatement, sensitive: Boolean): String

def emitReferenceNoOverrides(that: DeclarationStatement): String

def emitSignals(): Unit

def emitSubComponents(openSubIo: HashSet[BaseType]): Unit

def emitSynchronous(component: Component, group: SyncGroup): Unit

val endModule: StringBuilder

val enumDebugStringList: ArrayBuffer[(SpinalEnumCraft[_ <: SpinalEnum], String, Int)]

def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

val expressionToWrap: LinkedHashSet[Expression]

def fillExpressionToWrap(): Unit

def getBaseTypeSignalInitBoot(signal: BaseType): String

def getBaseTypeSignalRandBoot(signal: BaseType): String

final def getClass(): Class[_]

def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

def getTrace(): ComponentEmitterTrace

def hashCode(): Int

def idToBits[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String

val initials: ArrayBuffer[LeafStatement]