HardMap

final def !=(arg0: Any): Boolean

def ##(right: Data): Bits

Concatenation between two signals

final def ##(): Int

def #*(count: Int): Bits

Return the count time concatenation of the signal.

final def ==(arg0: Any): Boolean

def IFparent: Data

var _spinalTags: LinkedHashSet[SpinalTag]

def add[T <: Data](key: NamedType[T]): Unit

def addAttribute(attribute: Attribute): HardMap.this.type

def addAttribute(name: String, value: Int): HardMap.this.type

def addAttribute(name: String, value: String): HardMap.this.type

def addAttribute(name: String): HardMap.this.type

def addTag[T <: SpinalTag](spinalTag: T): HardMap.this.type

def addTags(h: SpinalTag, tail: SpinalTag*): HardMap.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): HardMap.this.type

def allowDirectionLessIo(): HardMap.this.type

Allow a signal of an io Bundle to be directionless.

def allowOverride(): HardMap.this.type

Allow a signal to be overridden.

def allowPartialyAssigned(): HardMap.this.type

Allow a register to be partially assigned

def allowPruning(): HardMap.this.type

def allowSimplifyIt(): HardMap.this.type

def allowUnsetRegToAvoidLatch(): HardMap.this.type

Allow a register to have only an init (no assignments)

def apply[T <: Data](key: NamedType[T]): T

def as[T <: Data](dataType: HardType[T]): T

def asBits: Bits

Cast signal to Bits

def asData: Data

def asInOut(): HardMap.this.type

Set a signal as inout

def asInput(): HardMap.this.type

Set a data as input

final def asInstanceOf[T0]: T0

def asOutput(): HardMap.this.type

Set a data as output

def assignDontCare(): HardMap.this.type

Assign the default 'x' value to all signals composing this type.

def assignDontCareToUnasigned(): HardMap.this.type

def assignFormalRandom(kind: RandomExpKind): Unit

final def assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit

def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit

def assignFromBits(bits: Bits): Unit

def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit

def assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

def assignUnassignedByName(that: MultiData): Unit

def clearAll(): HardMap.this.type

Clear all bits to False and return itself

def clone(): Data

def component: Component

final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

var compositeAssign: Assignable

def copyDirectionOfImpl(that: Data): HardMap.this.type

def dirString(): String

def dontSimplifyIt(): HardMap.this.type

def elements: ArrayBuffer[(String, Data)]

var elementsCache: ArrayBuffer[(String, Data)]

def elementsString: String

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def find(name: String): Data

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def flatten: Seq[BaseType]

def flattenForeach(body: (BaseType) ⇒ Unit): Unit

def flattenLocalName: Seq[String]

def flip(): HardMap.this.type

Flip the direction of the signal.

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def freeze(): HardMap.this.type

def getAheadValue(): HardMap.this.type

For a register, get the value it will have at the next clock, as a combinational signal.

def getBitsWidth: Int

Return the width of the data

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

Get current component with all parents

def getDirection: IODirection

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getPath(from: Component, to: Component): Seq[Component]

def getRealSource: Any

def getRealSourceNoRec: Any

def getRefOwnersChain(): List[Any]

def getRootParent: Data

def getRtlPath(separator: String = "/"): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

def getTagsOf[T <: SpinalTag]()(implicit tag: ClassTag[T]): Iterable[T]

def getZero: HardMap.this.type

Create a signal set to 0

var globalData: GlobalData

def hardMapAssign(that: HardMap)(f: (Data, Data) ⇒ Unit): Unit

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

final def initFrom(that: AnyRef, target: AnyRef = this): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

def isAnalog: Boolean

def isComb: Boolean

def isCompletelyUnnamed: Boolean

def isDirectionLess: Boolean

def isEmptyOfTag: Boolean

def isInOut: Boolean

def isInput: Boolean

def isInputOrInOut: Boolean

final def isInstanceOf[T0]: Boolean

final def isNamed: Boolean

def isOutput: Boolean

def isOutputOrInOut: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReg: Boolean

def isRegOnAssign: Boolean

def isUnnamed: Boolean

def keyToName(key: Any): String

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noBackendCombMerge(): HardMap.this.type

Put the combinatorial logic driving this signal in a separate process

def noCombLoopCheck(): HardMap.this.type

Disable combinatorial loop checking for this Data

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): HardMap.this.type

var parent: Data

var parentScope: ScopeStatement

def pull(propagateName: Boolean): HardMap.this.type

def pull(): HardMap.this.type

Pull a signal to the top level (use for debugging)

def purify(): HardMap.this.type

def randBoot(u: Unit): HardMap.this.type

Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

var refOwner: RefOwnerType

def reflectNames(): Unit

def removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): HardMap.this.type

def removeDataAssignments(): HardMap.this.type

def removeInitAssignments(): HardMap.this.type

def removeTag(spinalTag: SpinalTag): HardMap.this.type

def removeTags(tags: Iterable[SpinalTag]): HardMap.this.type

def resized: HardMap.this.type

Return a version of the signal which is allowed to be automatically resized where needed.

def rootIF(): Interface

root interface

def rootIFList(): List[Interface]

def rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]

var scalaTrace: Throwable

def setAll(): HardMap.this.type

Set all bits to True and return itself

def setAsAnalog(): HardMap.this.type

def setAsComb(): HardMap.this.type

Set baseType to Combinatorial

def setAsDirectionLess(): HardMap.this.type

Remove the direction (in, out, inout) to a signal

def setAsReg(): HardMap.this.type

Set baseType to reg

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): HardMap.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): HardMap.this.type

def setCompositeName(nameable: Nameable, postfix: String): HardMap.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): HardMap.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): HardMap.this.type

def setCompositeName(nameable: Nameable): HardMap.this.type

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): HardMap.this.type

def setName(name: String, namePriority: Byte): HardMap.this.type

def setName(name: String, weak: Boolean): HardMap.this.type

def setName(name: String): HardMap.this.type

def setNameAsWeak(): HardMap.this.type

def setOutputAsReg(): HardMap.this.type

Recursively set baseType to reg only for output

def setPartialName(name: String, namePriority: Byte, owner: Any): HardMap.this.type

def setPartialName(name: String, namePriority: Byte): HardMap.this.type

def setPartialName(name: String, weak: Boolean): HardMap.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): HardMap.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): HardMap.this.type

def setPartialName(name: String): HardMap.this.type

def setPartialName(owner: Nameable, name: String): HardMap.this.type

def setPartialName(owner: Nameable): HardMap.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): HardMap.this.type

def setWeakName(name: String): HardMap.this.type

def spinalTags: LinkedHashSet[SpinalTag]

val storage: LinkedHashMap[NamedType[Data], Data]

final def synchronized[T0](arg0: ⇒ T0): T0

def toIo(): HardMap.this.type

def toMuxInput[T <: Data](muxOutput: T): T

def toString(): String

def unfreeze(): HardMap.this.type

def unsetName(): HardMap.this.type

def update[T <: Data](key: NamedType[T], value: T): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def wrapNext(): HardMap.this.type

def zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)] = ArrayBuffer()): ArrayBuffer[(BaseType, BaseType)]

def asDirectionLess(): HardMap.this.type

def finalize(): Unit

def genIf(cond: Boolean): HardMap.this.type

Generate this if condition is true