Vec
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package core
Concatenation between two signals
Concatenation between two signals
Return the count time concatenation of the signal.
Return the count time concatenation of the signal.
Allow a signal of an io Bundle to be directionless.
Allow a signal of an io Bundle to be directionless.
Allow a signal to be overridden.
Allow a signal to be overridden.
Allow a register to be partially assigned
Allow a register to be partially assigned
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
Access an element of the vector by an UInt index
Access an element of the vector by an Int index
Access an element of the vector by an Int index
Cast signal to Bits
Set a signal as inout
Set a data as input
Set a data as output
Assign the default 'x' value to all signals composing this type.
Assign the default 'x' value to all signals composing this type.
Clear all bits to False
Clear all bits to False
Flip the direction of the signal.
For a register, get the value it will have at the next clock, as a combinational signal.
For a register, get the value it will have at the next clock, as a combinational signal.
Return the width of the data
Get current component with all parents
Get current component with all parents
Create a signal set to 0
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
Access an element of the vector by a oneHot value
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Return a version of the signal which is allowed to be automatically resized where needed.
Return a version of the signal which is allowed to be automatically resized where needed.
The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.
root interface
root interface
(Changed in version 2.9.0) The behavior of scanRight has changed. The previous behavior can be reproduced with scanRight.reverse.
Set all bits to True
Set all bits to True
Set baseType to Combinatorial
Remove the direction (in, out, inout) to a signal
Set baseType to reg
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
(Changed in version 2.9.0) transpose throws an IllegalArgumentException if collections are not uniformly sized.
(Since version ???) use setAsDirectionLess instead
(Since version ) see corresponding Javadoc for more information.
Generate this if condition is true
Generate this if condition is true
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
A
Vecis a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single nameVecDocumentation