DataPimper

final def !=(arg0: Any): Boolean

final def ##(): Int

def :=(that: T)(implicit loc: Location): Unit

Standard hardware assignment, equivalent to <= in VHDL/Verilog

def <>(that: T)(implicit loc: Location): Unit

Automatic connection between two hardware signals or two bundles of the same type.

def =/=(that: T): Bool

isNotEqualTo comparison between two hardware signals

def =::=(that: T): Bool

final def ==(arg0: Any): Boolean

def ===(that: T): Bool

isEqualTo comparison between two hardware signals

def \(that: T): T

Use as \= to have the same behavioral as VHDL variable

val _data: T

final def asInstanceOf[T0]: T0

def clone(): AnyRef

def copyDirectionOf(that: T): Unit

def default(that: ⇒ T): T

Set a default value to a signal.

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

final def getClass(): Class[_]

def hashCode(): Int

def init(that: T): T

Set initial value of the signal

def initNull(that: T): T

Set initial value only if that is not null

def initZero(): T

Set initial value as 0

final def isInstanceOf[T0]: Boolean

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def switchAssign[T2 <: BaseType](sel: T2)(mappings: (Any, T)*): Unit

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit