GB

~~BigIntBuilder~~ ~~IntBuilder~~

GHz

BigDecimalBuilder DoubleBuilder IntBuilder

GenerationFlags

core

Generic

core

GiB

BigIntBuilder IntBuilder

GlobalData

core

GlobalDataUser

core

GraphUtils

internals

genIf

Data

genVhdlPkg

SpinalConfig

generate

SpinalConfig BooleanPimped

generateAsBlackBox

Mem

generateSystemVerilog

SpinalConfig

generateUnblackboxableError

MemBlackboxingPolicy

generateVerilog

SpinalConfig

generateVhdl

SpinalConfig

generatedSourcesPaths

SpinalReport

generic

Ram_1w_1ra Ram_1w_1rs Ram_1wors Ram_1wrs Ram_2c_1w_1rs Ram_2wrs

genericElements

BlackBox

get

GlobalData

getAllIo

Component

getAllTrue

BitVector Bits SInt UInt

getBaseTypeSignalInitialisation

ComponentEmitterVerilog ComponentEmitterVhdl

getBitVector

BitVectorBitAccessFixed BitVectorBitAccessFloating BitVectorRangedAccessFixed BitVectorRangedAccessFloating SubAccess

getBitsStringOn

BitVectorLiteral BoolLiteral BoolPoison

getBitsWidth

BitVector Bool Data DataWrapper HardType MultiData SpinalEnumCraft

getClockDomainDriver

ClockDomain

getClockDomainTag

ClockDomain

getComponent

Data

getComponents

Data

getDefinition

EnumLiteral EnumPoison SpinalEnumCraft AnalogDriverEnum BinaryMultiplexerEnum CastBitsToEnum CastEnumToEnum EnumEncoded MultiplexerEnum Equal NotEqual PastEnum

getDisplayName

Component Nameable

getDrivingReg

BaseType

getElement

SpinalEnumEncoding binaryOneHot binarySequential inferred native

getElseNull

ArrayManager

getEncoding

EnumEncoded InferableEnumEncodingImpl

getErrorCount

SpinalError

getFactory

B BitVectorLiteralFactory S U

getGeneric

BlackBox

getGroupedIO

Component

getHeader

VhdlVerilogBase

getInstanceCounter

ContextUser GlobalData

getLiteralFactory

Mul ShiftLeftByInt ShiftLeftByUInt ShiftLeftByInt ShiftLeftByUInt Mul ShiftLeftByInt ShiftLeftByUInt Mul ShiftLeftByInt ShiftLeftByUInt Resize ResizeBits ResizeSInt ResizeUInt

getMax

ClockFrequency DivisionRate FixedDivisionRate FixedFrequency UnknownDivisionRate UnknownFrequency

getMaxAssignedBits

AssignmentExpression BitAssignmentFixed BitAssignmentFloating RangedAssignmentFixed RangedAssignmentFloating

getMin

ClockFrequency DivisionRate FixedDivisionRate FixedFrequency UnknownDivisionRate UnknownFrequency

getMinAssignedBits

AssignmentExpression BitAssignmentFixed BitAssignmentFloating RangedAssignmentFixed RangedAssignmentFloating

getMode

Nameable

getName

Attribute AttributeFlag AttributeString Nameable NameableByComponent

getOrDefault

ComponentEmitter

getOrdredNodeIo

Component

getParentsPath

Component

getPartialName

Nameable

getPath

Component

getReEncodingFuntion

VerilogBase VhdlBase

getRealSource

Assignable

getRealSourceNoRec

Assignable Data VecAccessAssign

getRefOwnersChain

OwnableRef

getRootParent

Data

getScalaLocationLong

ScalaLocated

getScalaLocationShort

ScalaLocated

getScalaTrace

ScalaLocated

getSingleDriver

BaseType

getTag

SpinalTagReady

getTags

SpinalTagReady

getThrowable

GlobalData

getTrace

ComponentEmitterVerilog ComponentEmitterVhdl

getTypeObject

Bits Bool EnumLiteral EnumPoison MemReadAsync MemReadSync MemReadWrite SInt SpinalEnumCraft UInt AnalogDriverBits AnalogDriverBool AnalogDriverEnum AnalogDriverSInt AnalogDriverUInt BinaryMultiplexerBits BinaryMultiplexerBool BinaryMultiplexerEnum BinaryMultiplexerSInt BinaryMultiplexerUInt BitAssignmentFixed BitAssignmentFloating BitsBitAccessFixed BitsBitAccessFloating BitsLiteral BitsRangedAccessFixed BitsRangedAccessFloating BoolLiteral BoolPoison CastBitsToEnum CastBitsToSInt CastBitsToUInt CastBoolToBits CastEnumToBits CastEnumToEnum CastSIntToBits CastSIntToUInt CastUIntToBits CastUIntToSInt Expression MultiplexerBits MultiplexerBool MultiplexerEnum MultiplexerSInt MultiplexerUInt Equal NotEqual And Cat Not Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Xor And Equal Not NotEqual Or Xor Equal NotEqual Changed Fell InitState PastBits PastBool PastEnum PastSInt PastUInt Rose Stable Add And Div Minus Mod Mul Not Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Smaller SmallerOrEqual Sub Xor Add And Div Mod Mul Not Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Smaller SmallerOrEqual Sub Xor RangedAssignmentFixed RangedAssignmentFloating ResizeBits ResizeSInt ResizeUInt SIntBitAccessFixed SIntBitAccessFloating SIntLiteral SIntRangedAccessFixed SIntRangedAccessFloating SwitchStatementKeyBool UIntBitAccessFixed UIntBitAccessFloating UIntLiteral UIntRangedAccessFixed UIntRangedAccessFloating

getTypeString

Bundle

getUnusedName

NamingScope

getValue

ClockFrequency DivisionRate FixedDivisionRate FixedFrequency UnknownDivisionRate UnknownFrequency EnumLiteral EnumPoison SpinalEnumEncoding binaryOneHot binarySequential inferred BitVectorLiteral BoolLiteral BoolPoison Literal native

getWidth

MaskedLiteral Mem MemReadAsync MemReadSync MemReadWrite MemWrite SpinalEnumEncoding binaryOneHot binarySequential inferred BitVectorLiteral BitVectorRangedAccessFixed BitVectorRangedAccessFloating RangedAssignmentFixed RangedAssignmentFloating Resize WidthProvider Widthable native

getWidthNoInferation

BitVector

getWidthStringNoInferation

BitVector

getZero

Bits Bool Data DataWrapper MultiData SInt SpinalEnumCraft UInt

getZeroUnconstrained

BitVector Bits SInt UInt

gitHash

Info

globalData

GlobalDataUser PhaseContext

globalPrefix

SpinalConfig

globalScope

PhaseContext