OWNER_PREFIXED
Nameable
Operator
internals
Or
BitVector Bits Bool SInt UInt
OverridedEqualsHashCode
core
OwnableRef
core
offset
BitVectorRangedAccessFloating RangedAssignmentFloating
oldest
SafeStack
onActiveEdges
SimClockDomainPimper
onEachAttributes
SpinalTagReady
onEdges
SimClockDomainPimper
onFallingEdges
SimClockDomainPimper
onNextSampling
SimClockDomainPimper
onRisingEdges
SimClockDomainPimper
onSamplings
SimClockDomainPimper SimStatics
onUnblackboxable
MemBlackboxingPolicy blackboxAll blackboxAllWhatsYouCan blackboxOnlyIfRequested blackboxRequestedAndUninferable
oneFilePerComponent
SpinalConfig
oneHotAccess
Vec
onlyStdLogicVectorAtTopLevelIo
SpinalConfig
opImplAsCast
ComponentEmitterVhdl
opName
Bits Bool EnumLiteral EnumPoison MemReadAsync MemReadSync MemReadWrite SInt SpinalEnumCraft UInt AnalogDriverBits AnalogDriverBool AnalogDriverEnum AnalogDriverSInt AnalogDriverUInt BinaryMultiplexerBits BinaryMultiplexerBool BinaryMultiplexerEnum BinaryMultiplexerSInt BinaryMultiplexerUInt BitAssignmentFixed BitAssignmentFloating BitsBitAccessFixed BitsBitAccessFloating BitsLiteral BitsRangedAccessFixed BitsRangedAccessFloating BoolLiteral BoolPoison CastBitsToEnum CastBitsToSInt CastBitsToUInt CastBoolToBits CastEnumToBits CastEnumToEnum CastSIntToBits CastSIntToUInt CastUIntToBits CastUIntToSInt Expression MultiplexerBits MultiplexerBool MultiplexerEnum MultiplexerSInt MultiplexerUInt And Cat Equal Not NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Xor And Equal Not NotEqual Or Xor Equal NotEqual Changed Fell InitState PastBits PastBool PastEnum PastSInt PastUInt Rose Stable Add And Div Equal Minus Mod Mul Not NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Smaller SmallerOrEqual Sub Xor Add And Div Equal Mod Mul Not NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Smaller SmallerOrEqual Sub Xor RangedAssignmentFixed RangedAssignmentFloating ResizeBits ResizeSInt ResizeUInt SIntBitAccessFixed SIntBitAccessFloating SIntLiteral SIntRangedAccessFixed SIntRangedAccessFloating SwitchStatementKeyBool UIntBitAccessFixed UIntBitAccessFloating UIntLiteral UIntRangedAccessFixed UIntRangedAccessFloating
openSubIo
ComponentEmitter
operatorImplAsBinaryOperator
ComponentEmitterVerilog ComponentEmitterVhdl
operatorImplAsBinaryOperatorLeftSigned
ComponentEmitterVerilog
operatorImplAsBinaryOperatorSigned
ComponentEmitterVerilog
operatorImplAsBinaryOperatorStdCast
ComponentEmitterVhdl
operatorImplAsBitsToEnum
ComponentEmitterVhdl
operatorImplAsCat
ComponentEmitterVerilog
operatorImplAsEnumToBits
ComponentEmitterVhdl
operatorImplAsEnumToEnum
ComponentEmitterVerilog ComponentEmitterVhdl
operatorImplAsMux
ComponentEmitterVerilog
operatorImplAsNoTransformation
ComponentEmitterVerilog
operatorImplAsUnaryOperator
ComponentEmitterVerilog ComponentEmitterVhdl
operatorImplResize
ComponentEmitterVerilog
operatorImplResizeSigned
ComponentEmitterVerilog
optimisationLevel
SpinalVerilatorBackendConfig
orR
BitVector
otherwise
WhenContext
out
BitAssignmentFixed BitAssignmentFloating RangedAssignmentFixed RangedAssignmentFloating core
outFile
PhaseVerilog PhaseVhdl
outWithNull
core
outputsToBufferize
ComponentEmitter