sim

Type Members

implicit class SimBaseTypePimper extends AnyRef

Add implicit function to BaseType for simulation
implicit class SimBitVectorPimper extends AnyRef

Add implicit function to BitVector
implicit class SimBitsPimper extends AnyRef

Add implicit function to Bits
implicit class SimBoolPimper extends AnyRef

Add implicit function to Bool
implicit class SimClockDomainPimper extends AnyRef

Add implicit function to ClockDomain
class SimCompiled[T <: Component] extends AnyRef

Run simulation
case class SimConfigLegacy[T <: Component](_rtlGen: Option[() ⇒ T] = None, _spinalConfig: SpinalConfig = SpinalConfig(), _spinalReport: Option[SpinalReport[T]] = None) extends Product with Serializable

Legacy simulation configuration
implicit class SimDataPimper[T <: Data] extends AnyRef

Add implicit function to Data
implicit class SimEnumPimper[T <: SpinalEnum] extends AnyRef

Add implicit function to Enum
implicit class SimSIntPimper extends AnyRef

Add implicit function to SInt
implicit class SimUIntPimper extends AnyRef

Add implicit function to UInt
case class SpinalSimConfig(_workspacePath: String = ..., _workspaceName: String = null, _waveDepth: Int = 0, _spinalConfig: SpinalConfig = SpinalConfig(), _optimisationLevel: Int = 0, _simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), _additionalRtlPath: ArrayBuffer[String] = ArrayBuffer[String](), _waveFormat: WaveFormat = WaveFormat.NONE) extends Product with Serializable

SpinalSim configuration
case class SpinalVerilatorBackendConfig[T <: Component](rtl: SpinalReport[T], waveFormat: WaveFormat = WaveFormat.NONE, workspacePath: String = "./", workspaceName: String = null, vcdPath: String = null, vcdPrefix: String = null, waveDepth: Int = 0, optimisationLevel: Int = 2, simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String]()) extends Product with Serializable

Backend configuration for verilator
class SwapTagPhase extends PhaseNetlist

Swap all oldTag with newTag
type suspendable = sim.suspendable

Value Members

object DoClock

Generate a clock
object DoReset

Execute a reset sequence
object ForkClock

Fork the DoClock
def SimConfig: SpinalSimConfig
object SimPublic extends SpinalTag

Tag SimPublic
object SimSpeedPrinter

Print the simulation speed
object SimStatics
object SimTimeout

Create a Timeout for the simulation
object SimWorkspace

Simulation Workspace
object SpinalVerilatorBackend

Backend verilator
object SpinalVerilatorSim
def delayed(delay: Long)(body: ⇒ Unit): Unit
def disableSimWave(): Unit
def enableSimWave(): Unit
def fork(body: ⇒ Unit): SimThread

Fork
def forkJoin(bodys: () ⇒ Unit*): Unit
def forkSensitive(trigger: ⇒ Any)(block: ⇒ Unit): Unit
def forkSensitive(triggers: Data*)(block: ⇒ Unit): Unit
def forkSensitive(block: ⇒ Unit): Unit
def forkSensitiveWhile(block: ⇒ Boolean): Unit
def setBigInt(bt: BaseType, value: BigInt): Unit

Set a BigInt value to a BaseType
def setLong(bt: BaseType, value: Long): Unit

Set a long value to a BaseType
def simDeltaCycle(): Long
def simFailure(message: String = ""): Unit
def simSuccess(): Unit

Success/Failure simulation
def simTime(): Long

Return the current simulation time
def sleep(cycles: Long): Unit

Sleep / WaitUntil
def waitUntil(cond: ⇒ Boolean): Unit

Deprecated Value Members

def SimConfig[T <: Component](rtl: SpinalReport[T]): SimConfigLegacy[T]

Annotations
@deprecated
Deprecated
(Since version ???) Use SimConfig.???.compile(new Dut) instead
def SimConfig[T <: Component](rtl: ⇒ T): SimConfigLegacy[T]

Annotations
@deprecated
Deprecated
(Since version ???) Use SimConfig.???.compile(new Dut) instead

package sim

Type Members

implicit class SimBaseTypePimper extends AnyRef

implicit class SimBitVectorPimper extends AnyRef

implicit class SimBitsPimper extends AnyRef

implicit class SimBoolPimper extends AnyRef

implicit class SimClockDomainPimper extends AnyRef

class SimCompiled[T <: Component] extends AnyRef

case class SimConfigLegacy[T <: Component](_rtlGen: Option[() ⇒ T] = None, _spinalConfig: SpinalConfig = SpinalConfig(), _spinalReport: Option[SpinalReport[T]] = None) extends Product with Serializable

implicit class SimDataPimper[T <: Data] extends AnyRef

implicit class SimEnumPimper[T <: SpinalEnum] extends AnyRef

implicit class SimSIntPimper extends AnyRef

implicit class SimUIntPimper extends AnyRef

class SwapTagPhase extends PhaseNetlist

type suspendable = sim.suspendable

Value Members

object DoClock

object DoReset

object ForkClock

def SimConfig: SpinalSimConfig

object SimPublic extends SpinalTag

object SimSpeedPrinter

object SimStatics

object SimTimeout

object SimWorkspace

object SpinalVerilatorBackend

object SpinalVerilatorSim

def delayed(delay: Long)(body: ⇒ Unit): Unit

def disableSimWave(): Unit

def enableSimWave(): Unit

def fork(body: ⇒ Unit): SimThread

def forkJoin(bodys: () ⇒ Unit*): Unit

def forkSensitive(trigger: ⇒ Any)(block: ⇒ Unit): Unit

def forkSensitive(triggers: Data*)(block: ⇒ Unit): Unit

def forkSensitive(block: ⇒ Unit): Unit

def forkSensitiveWhile(block: ⇒ Boolean): Unit

def setBigInt(bt: BaseType, value: BigInt): Unit

def setLong(bt: BaseType, value: Long): Unit

def simDeltaCycle(): Long

def simFailure(message: String = ""): Unit

def simSuccess(): Unit

def simTime(): Long

def sleep(cycles: Long): Unit

def waitUntil(cond: ⇒ Boolean): Unit

Deprecated Value Members

def SimConfig[T <: Component](rtl: SpinalReport[T]): SimConfigLegacy[T]

def SimConfig[T <: Component](rtl: ⇒ T): SimConfigLegacy[T]

Inherited from AnyRef

Inherited from Any

Ungrouped