Class

spinal.core.internals

PhaseVerilog

Related Doc: package internals

Permalink

class PhaseVerilog extends PhaseMisc with VerilogBase

Linear Supertypes
VerilogBase, VhdlVerilogBase, PhaseMisc, Phase, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. PhaseVerilog
  2. VerilogBase
  3. VhdlVerilogBase
  4. PhaseMisc
  5. Phase
  6. AnyRef
  7. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new PhaseVerilog(pc: PhaseContext, report: SpinalReport[_])

    Permalink

Value Members

  1. final def !=(arg0: Any): Boolean

    Permalink
    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

    Permalink
    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

    Permalink
    Definition Classes
    AnyRef → Any

  4. val allocateAlgoIncrementaleBase: Int

    Permalink

  5. final def asInstanceOf[T0]: T0

    Permalink
    Definition Classes
    Any

  6. def clone(): AnyRef

    Permalink
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @HotSpotIntrinsicCandidate() @throws( ... )

  7. def compile(component: Component): () ⇒ String

    Permalink

  8. def emitClockEdge(clock: String, edgeKind: EdgeKind): String

    Permalink
    Definition Classes
    VerilogBase

  9. def emitCommentAttributes(attributes: Iterable[Attribute]): String

    Permalink
    Definition Classes
    VerilogBase

  10. def emitCommentEarlyAttributes(attributes: Iterable[Attribute]): String

    Permalink
    Definition Classes
    VerilogBase

  11. def emitDirection(baseType: BaseType): String

    Permalink
    Definition Classes
    VerilogBase

  12. def emitEnumLiteral[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding, prefix: String = "`"): String

    Permalink
    Definition Classes
    VerilogBase

  13. def emitEnumPackage(out: FileWriter): Unit

    Permalink

  14. def emitEnumType(senum: SpinalEnum, encoding: SpinalEnumEncoding, prefix: String = "`"): String

    Permalink
    Definition Classes
    VerilogBase

  15. def emitEnumType[T <: SpinalEnum](senum: SpinalEnumCraft[T], prefix: String): String

    Permalink
    Definition Classes
    VerilogBase

  16. def emitExpressionWrap(e: Expression, name: String, nature: String): String

    Permalink
    Definition Classes
    VerilogBase

  17. def emitExpressionWrap(e: Expression, name: String): String

    Permalink
    Definition Classes
    VerilogBase

  18. def emitFunctions(component: Component, ret: StringBuilder): Unit

    Permalink

  19. def emitRange(node: WidthProvider): String

    Permalink
    Definition Classes
    VerilogBase

  20. def emitResetEdge(reset: String, polarity: Polarity): String

    Permalink
    Definition Classes
    VerilogBase

  21. def emitStructType(struct: SpinalStruct): String

    Permalink
    Definition Classes
    VerilogBase

  22. def emitSyntaxAttributes(attributes: Iterable[Attribute]): String

    Permalink
    Definition Classes
    VerilogBase

  23. def emitType(e: Expression): String

    Permalink
    Definition Classes
    VerilogBase

  24. val emitedComponent: Map[ComponentEmitterTrace, Component]

    Permalink

  25. val emitedComponentRef: ConcurrentHashMap[Component, Component]

    Permalink

  26. final def eq(arg0: AnyRef): Boolean

    Permalink
    Definition Classes
    AnyRef

  27. def equals(arg0: Any): Boolean

    Permalink
    Definition Classes
    AnyRef → Any

  28. def expressionAlign(net: String, section: String, name: String): String

    Permalink
    Definition Classes
    VerilogBase

  29. final def getClass(): Class[_]

    Permalink
    Definition Classes
    AnyRef → Any
    Annotations
    @HotSpotIntrinsicCandidate()

  30. def getReEncodingFuntion(spinalEnum: SpinalEnum, source: SpinalEnumEncoding, target: SpinalEnumEncoding): String

    Permalink
    Definition Classes
    VerilogBase

  31. var globalPrefix: String

    Permalink
    Definition Classes
    VerilogBase

  32. def hasNetlistImpact: Boolean

    Permalink
    Definition Classes
    PhaseMisc → Phase

  33. def hashCode(): Int

    Permalink
    Definition Classes
    AnyRef → Any
    Annotations
    @HotSpotIntrinsicCandidate()

  34. def impl(pc: PhaseContext): Unit

    Permalink
    Definition Classes
    PhaseVerilog → Phase

  35. final def isInstanceOf[T0]: Boolean

    Permalink
    Definition Classes
    Any

  36. final def ne(arg0: AnyRef): Boolean

    Permalink
    Definition Classes
    AnyRef

  37. final def notify(): Unit

    Permalink
    Definition Classes
    AnyRef
    Annotations
    @HotSpotIntrinsicCandidate()

  38. final def notifyAll(): Unit

    Permalink
    Definition Classes
    AnyRef
    Annotations
    @HotSpotIntrinsicCandidate()

  39. var outFile: FileWriter

    Permalink

  40. val romCache: HashMap[String, String]

    Permalink

  41. def rtlName: String

    Permalink

  42. def signalNeedProcess(baseType: BaseType): Boolean

    Permalink
    Definition Classes
    VerilogBase

  43. final def synchronized[T0](arg0: ⇒ T0): T0

    Permalink
    Definition Classes
    AnyRef

  44. def targetPath: String

    Permalink

  45. val theme: Tab2

    Permalink
    Definition Classes
    VerilogBase

  46. def toString(): String

    Permalink
    Definition Classes
    AnyRef → Any

  47. val usedDefinitionNames: HashSet[String]

    Permalink

  48. final def wait(arg0: Long, arg1: Int): Unit

    Permalink
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  49. final def wait(arg0: Long): Unit

    Permalink
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  50. final def wait(): Unit

    Permalink
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit

    Permalink
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @Deprecated @deprecated @throws( classOf[java.lang.Throwable] )
    Deprecated

    (Since version ) see corresponding Javadoc for more information.

Inherited from VerilogBase

Inherited from VhdlVerilogBase

Inherited from PhaseMisc

Inherited from Phase

Inherited from AnyRef

Inherited from Any

Ungrouped