I2CMasterHAL

Value Members

1. final def !=(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

2. final def ##(): Int

   

   Definition Classes

   AnyRef → Any

3. final def ==(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

4. def addPrePopTask(task: () ⇒ Unit): ArrayBuffer[() ⇒ Unit]

   

   Definition Classes

   Component

5. final def asInstanceOf[T0]: T0

   

   Definition Classes

   Any

6. val children: ArrayBuffer[Component]

   

   Definition Classes

   Component

7. val clockDomain: ClockDomain

   

   Definition Classes

   Component

8. def clone(): AnyRef

   

   Attributes

   protected[java.lang]

   Definition Classes

   AnyRef

   Annotations

   @throws( ... )

9. val counterBit: Area { ... /* 3 definitions in type refinement */ }

   

   Counter of bit write/read.

   Counter of bit write/read. MSB is send first on the I2C bus so counter goes from dataWdith to 0

10. var definitionName: String

    

    Definition Classes

    Component

11. def delayedInit(body: ⇒ Unit): Unit

    

    Definition Classes

    Component → DelayedInit

12. final def eq(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

13. def equals(arg0: Any): Boolean

    

    Definition Classes

    AnyRef → Any

14. def finalize(): Unit

    

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

15. def forEachNameables(doThat: (Any) ⇒ Unit): Unit

    

    Definition Classes

    Nameable

16. def getAllIo: Set[BaseType]

    

    Definition Classes

    Component

17. final def getClass(): Class[_]

    

    Definition Classes

    AnyRef → Any

18. def getDisplayName(): String

    

    Definition Classes

    Component → Nameable

19. def getGroupedIO(ioBundleBypass: Boolean): Seq[Data]

    

    Definition Classes

    Component

20. def getName(): String

    

    Definition Classes

    NameableByComponent → Nameable

21. def getParentsPath(sep: String): String

    

    Definition Classes

    Component

22. def getPath(sep: String): String

    

    Definition Classes

    Component

23. def getScalaLocationLong: String

    

    Definition Classes

    ScalaLocated

24. def getScalaLocationShort: String

    

    Definition Classes

    ScalaLocated

25. val globalData: GlobalData

    

    Definition Classes

    GlobalDataUser

26. def hashCode(): Int

    

    Definition Classes

    AnyRef → Any

27. val io: I2CMasterHALio

    

28. final def isInstanceOf[T0]: Boolean

    

    Definition Classes

    Any

29. def isNamed: Boolean

    

    Definition Classes

    Nameable

30. def isUnnamed: Boolean

    

    Definition Classes

    Nameable

31. def nameChangeEvent(weak: Boolean): Unit

    

    Attributes

    protected

    Definition Classes

    Nameable

32. def nameElements(): Unit

    

    Definition Classes

    Component

33. final def ne(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

34. var nodes: ArrayBuffer[Node]

    

    Definition Classes

    Component

35. final def notify(): Unit

    

    Definition Classes

    AnyRef

36. final def notifyAll(): Unit

    

    Definition Classes

    AnyRef

37. val parent: Component

    

    Definition Classes

    Component

38. def parents(of: Component, list: List[Component]): List[Component]

    

    Definition Classes

    Component

39. def postPopEvent(): Unit

    

    Definition Classes

    Stackable

40. def postPushEvent(): Unit

    

    Definition Classes

    Component → Stackable

41. def prePopEvent(): Unit

    

    Definition Classes

    Component → Stackable

42. def readSM(sda: Bool, dataReceived: Bits): StateMachine { val sREAD: spinal.lib.fsm.State }

    

    Read a data on the I2C bus

    Read a data on the I2C bus

    sda

    : The read signal of the sda

    dataReceived

    : Register that will contains the data receveid

43. val sclGenerator: Area { ... /* 5 definitions in type refinement */ }

    

    Generate and manage the scl clock, signals to indicate the rising and falling edge of SCL as well as a signal to indicate when to execute a start/stop/restart operation

44. val scl_en: Bool

    

45. val scl_freeze: Bool

    

46. def setCompositeName(nameable: Nameable): Unit

    

    Definition Classes

    Nameable

47. def setDefinitionName(name: String): I2CMasterHAL.this.type

    

    Definition Classes

    Component

48. def setName(name: String, weak: Boolean): I2CMasterHAL.this.type

    

    Definition Classes

    Nameable

49. def setName(nameable: Nameable): Unit

    

    Definition Classes

    Nameable

50. def setWeakName(name: String): Nameable

    

    Definition Classes

    Nameable

51. val smMaster: StateMachine { ... /* 19 definitions in type refinement */ }

    

    Main state machine of the Master HAL

52. val smSynchSCL: StateMachine { ... /* 3 definitions in type refinement */ }

    

    State machine which synchronize all SCL signals of the different master in the case when several master drive the SCL.

53. final def synchronized[T0](arg0: ⇒ T0): T0

    

    Definition Classes

    AnyRef

54. def toString(): String

    

    Definition Classes

    Nameable → AnyRef → Any

55. val userCache: Map[AnyRef, Map[AnyRef, AnyRef]]

    

    Definition Classes

    Component

56. final def wait(): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

57. final def wait(arg0: Long, arg1: Int): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

58. final def wait(arg0: Long): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

59. def writeSM(wr_sda: Bool, data2Send: Bits, rd_sda: Bool = null): StateMachine { ... /* 2 definitions in type refinement */ }

    

    Write a data on the I2C

    Write a data on the I2C

    wr_sda

    : The write signal of the sda

    data2Send

    : Data that will be sent on the I2C

    rd_sda

    : If not null, the data write will be read to check if collision exist on the bus (multi master)