StreamPipe

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

val FULL: StreamPipe

Insert a stage that cut the valid, ready and payload signals through registers

val FULL_KEEP: StreamPipe

val HALF: StreamPipe

Insert a stage that cut all path, but divide the bandwidth by 2.

val HALF_KEEP: StreamPipe

val HALF_X2_KEEP: StreamPipe

val M2S: StreamPipe

Insert a stage that cut the valid and payload signals through registers

val M2S_KEEP: StreamPipe

val NONE: StreamPipe

Connect directly

val S2M: StreamPipe

Insert a stage that cut the ready path through a register

val S2M_KEEP: StreamPipe

final def asInstanceOf[T0]: T0

def clone(): AnyRef

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

final def getClass(): Class[_]

def hashCode(): Int

final def isInstanceOf[T0]: Boolean

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit