Stream
Related Docs:
object Stream
| package lib
Connect slaveStream <-/< masterStream.
Connect slaveStream <-/< masterStream. The valid/payload/ready path are cut by an register stage.
Connect slaveStream <-< masterStream.
Connect slaveStream <-< masterStream. The valid/payload path are cut by an register stage.
Connect slaveStream </< masterStream.
Connect slaveStream </< masterStream. The ready path is cut by an register stage.
Connect slaveStream << masterStream without any registering.
Connect masterStream >-> slaveStream.
Connect masterStream >-> slaveStream. The valid/payload path are cut by an register stage.
Connect masterStream >/-> slaveStream.
Connect masterStream >/-> slaveStream. The valid/payload/ready path are cut by an register stage.
Connect masterStream >/> slaveStream.
Connect masterStream >/> slaveStream. The ready path is cut by an register stage.
Connect masterStream >> slaveStream without any registering.
Like addFragmentLast(Bool), but instead of manually telling which values go together, let a counter do the job.
Like addFragmentLast(Bool), but instead of manually telling which values go together, let a counter do the job.
The counter will increment for each passing element. Last will be set high at the end of each revolution.
outStream = inStream.addFragmentLast(new Counter(5))
Convert this Stream to a fragmented Stream by adding a last bit.
Drive arbitration signals of this Stream from the provided Stream
A combinatorial stage doesn't do anything, but it is nice to separate signals for combinatorial transformations.
Block this when cond is False.
Block this when cond is False. Return the resulting Stream
Delay the stream by a given number of cycles.
Delay the stream by a given number of cycles.
Number of cycles to delay the stream
Delayed stream
Discard transactions when cond is True.
Discard transactions when cond is True.
This is the same as throwWhen() but with a semantically clearer function name. Prefer discardWhen() over throwWhen() for new designs.
Condition
The resulting Stream
Return True when a transaction occurs on the bus (valid && ready)
Return True when a transaction occurs on the bus (valid && ready)
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid may only be deasserted once the current payload was acknowledged.
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid may only be deasserted once the current payload was acknowledged.
Check that the payload does not change when valid is high and ready is low.
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid should be acknowledged in limited cycles.
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid should be acknowledged in limited cycles.
Check that the max cycles the interface would hold in stall.
Return a Stream that cut all path, but divide the bandwidth by 2.
Return a Stream that cut all path, but divide the bandwidth by 2.
The cost is (payload width + 2) flip-flops and the latency is 1.
Stop transactions on this when cond is True and return the resulting Stream.
Convert into master
Convert into master
Convert into slave
Convert into slave
Return True when the bus isn't stuck with a transaction (!isStall)
Are port directions set for a Master interface?
Are port directions set for a Master interface?
Return True when a transaction has appeared (first cycle)
Are port directions set for a Master interface?
Are port directions set for a Master interface?
Return True when a transaction is present on the bus but the ready signal is low
Return a stream that cut the valid and payload signals through registers.
Return a stream that cut the valid and payload signals through registers.
The cost is (payload width + 1) flip-flops and the latency is 1.
The name "m2s" comes from from the fact that the signals that flow
from Master-to-Slave are pipelined (namely ready and payload).
When true(the default), add the logic to allow to store an incoming payload when there is
no stored payload and the slave is not ready.
If false(the default), do not add tags on the payload signal for clock domain crossing.
An optional signal to set the valid register to 0.
When false(the default), do not add the logic to keep the slave side payload constant after the one cycle
when the slave consumed the payload.
If false(the default), do not add an attribute to avoid optimization of the slave side valid and payload.
If not null, a value to initialize the payload registers.
stage()
Return a Stream with payload calculated by a translate function.
Return a Stream with payload calculated by a translate function.
Modify the payload of the x stream, while preserving the valid and ready signals
Content of the transaction driven by the master, don't care when valid is 0.
Content of the transaction driven by the master, don't care when valid is 0.
Return a pipelined version of this Stream based on the provided arguments.
Return a pipelined version of this Stream based on the provided StreamPipe spec.
Connect this to an clock crossing fifo and return its pop stream
Connect this to a fifo and return its pop stream
Connect this to a zero latency fifo and return its pop stream
Connect this to a register constructed fifo and return its pop stream
Connect this to a fifo and return its pop stream and its occupancy
Connect this to a cross clock domain fifo and return its pop stream and its push side occupancy
Signal driven by the slave, indicating consumption of the payload, don't care when valid is 0.
Connect this to a new stream that only advances every n elements, thus repeating the input several times.
Connect this to a new stream that only advances every n elements, thus repeating the input several times.
A tuple with the resulting stream that duplicates the items and the counter, indicating how many times the current element has been repeated.
Return a stream that cut the ready path through a register.
Return a stream that cut the ready path through a register.
As long as the slave is ready, the valid and payload signal are passed without registering.
When the slave ready goes to low, the payload is stored and will be consumed later at the
first cycle of ready to high.
The cost is payload width + 1 flip-flops and payload width mux2. The latency is 0.
The name "s2m" comes from from the fact that the signal that flows
from Slave-to-Master is pipelined (namely valid).
An optional signal to set the valid register to 0.
If false(the default), do not add an attribute to avoid optimization of the slave side valid and payload signals.
Set as master interface
Set as master interface
Set a slave interface
Set a slave interface
Connect this to a new stream whose payload is n times as wide, but that only fires every n cycles.
Connect this to a new stream whose payload is n times as wide, but that only fires every n cycles. It introduces 0 to factor-1 cycles of latency. Mapping a stream into memory and mapping a slowed down stream into memory should yield the same result, thus the elements of the input will be written from high bits to low bits.
Connect this to a valid/payload register stage and return its output stream.
Connect this to a valid/payload register stage and return its output stream.
The cost is (payload width + 1) flip-flops and the latency is 1.
Equivalent to m2sPipe() but with "stage" name in the generated HDL.
Drop transaction of this when cond is False and return the resulting Stream.
Drop transactions of this when cond is True and return the resulting Stream.
Ignore the payload
Return a flow driven by this stream. Ready of ths stream is always high
Replace this stream's payload with another one
Change the payload's content type.
Change the payload's content type. The new type must have the same bit length as the current one.
Signal driven by the master, indicating payload present on the interface.
Signal driven by the master, indicating payload present on the interface.
(Since version ???) use setAsDirectionLess instead
Override it to define port directions for a master interface.
Override it to define port directions for a master interface.
This method must be overriden but not called. Calling this
method is not correct. Call setAsMaster() or intoMaster() instead.
This method is named asXxx but it does not return Xxx.
This method does not update isMasterInterface and isSlaveInterface.
Override it to define port directions for a master interface.
Override it to define port directions for a master interface.
If not overriden, defaults to the opposite port directions of asMaster().
This method can be overriden but not called. Calling this
method is not correct. Call setAsSlave() or intoSlave() instead.
This method is named asXxx but it does not return Xxx.
This method does not update isMasterInterface and isSlaveInterface.
(Since version ) see corresponding Javadoc for more information.
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
A simple interface with master payload
valid, slavereadyhandshake.When manually reading/driving the signals of a Stream keep in mind that:
validmay only be deasserted once the current payload was acknowledged. This meansvalidcan only toggle to 0 the cycle after a the slave did a read by asserting ready.readymay change at any time.validandreadyare asserted.validof a Stream must not depend onreadyin a combinatorial way and any path between the two must be registered.It is recommended that
validdoes not depend onreadyat all.Stream documentation