Class

spinal.lib.com.spi.ddr.SpiXdrMasterCtrl

MemoryMappingParameters

Related Doc: package SpiXdrMasterCtrl

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case class MemoryMappingParameters(ctrl: Parameters, cmdFifoDepth: Int = 32, rspFifoDepth: Int = 32, cpolInit: Boolean = false, cphaInit: Boolean = false, modInit: Int = 0, sclkToogleInit: Int = 0, ssSetupInit: Int = 0, ssHoldInit: Int = 0, ssDisableInit: Int = 0, ssActiveHighInit: Int = 0, xipInstructionModInit: Int = 0, xipAddressModInit: Int = 0, xipDummyModInit: Int = 0, xipPayloadModInit: Int = 0, xipConfigWritable: Boolean = true, xipEnableInit: Boolean = false, xipInstructionEnableInit: Boolean = true, xipInstructionDataInit: Int = 0x0B, xipDummyCountInit: Int = 1, xipDummyDataInit: Int = 0xFF, xip: XipBusParameters = null) extends Product with Serializable

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  1. MemoryMappingParameters
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Instance Constructors

  1. new MemoryMappingParameters(ctrl: Parameters, cmdFifoDepth: Int = 32, rspFifoDepth: Int = 32, cpolInit: Boolean = false, cphaInit: Boolean = false, modInit: Int = 0, sclkToogleInit: Int = 0, ssSetupInit: Int = 0, ssHoldInit: Int = 0, ssDisableInit: Int = 0, ssActiveHighInit: Int = 0, xipInstructionModInit: Int = 0, xipAddressModInit: Int = 0, xipDummyModInit: Int = 0, xipPayloadModInit: Int = 0, xipConfigWritable: Boolean = true, xipEnableInit: Boolean = false, xipInstructionEnableInit: Boolean = true, xipInstructionDataInit: Int = 0x0B, xipDummyCountInit: Int = 1, xipDummyDataInit: Int = 0xFF, xip: XipBusParameters = null)

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Value Members

  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. final def asInstanceOf[T0]: T0

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  5. def clone(): AnyRef

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  6. val cmdFifoDepth: Int

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  7. val cphaInit: Boolean

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  8. val cpolInit: Boolean

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  9. val ctrl: Parameters

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  10. final def eq(arg0: AnyRef): Boolean

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  11. def finalize(): Unit

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  12. final def getClass(): Class[_]

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  13. final def isInstanceOf[T0]: Boolean

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  14. val modInit: Int

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  15. final def ne(arg0: AnyRef): Boolean

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  16. final def notify(): Unit

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  17. final def notifyAll(): Unit

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  18. val rspFifoDepth: Int

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  19. val sclkToogleInit: Int

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  20. val ssActiveHighInit: Int

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  21. val ssDisableInit: Int

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  22. val ssHoldInit: Int

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  23. val ssSetupInit: Int

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  24. final def synchronized[T0](arg0: ⇒ T0): T0

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  25. final def wait(): Unit

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  26. final def wait(arg0: Long, arg1: Int): Unit

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  27. final def wait(arg0: Long): Unit

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  28. val xip: XipBusParameters

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  29. val xipAddressModInit: Int

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  30. val xipConfigWritable: Boolean

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  31. val xipDummyCountInit: Int

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  32. val xipDummyDataInit: Int

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  33. val xipDummyModInit: Int

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  34. val xipEnableInit: Boolean

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  35. val xipInstructionDataInit: Int

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  36. val xipInstructionEnableInit: Boolean

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  37. val xipInstructionModInit: Int

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  38. val xipPayloadModInit: Int

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Inherited from Serializable

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Inherited from Product

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