Class

spinal.lib.cpu.riscv.impl

RiscvCoreConfig

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case class RiscvCoreConfig(pcWidth: Int = 32, addrWidth: Int = 32, startAddress: Int = 0, bypassExecute0: Boolean = true, bypassExecute1: Boolean = true, bypassWriteBack: Boolean = true, bypassWriteBackBuffer: Boolean = true, collapseBubble: Boolean = true, branchPrediction: BranchPrediction = static, regFileReadyKind: RegFileReadKind = sync, fastFetchCmdPcCalculation: Boolean = true, dynamicBranchPredictorCacheSizeLog2: Int = 4, branchPredictorHistoryWidth: Int = 2, invalidInstructionIrqId: Int = 0, unalignedMemoryAccessIrqId: Int = 1) extends Product with Serializable

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Serializable, Serializable, Product, Equals, AnyRef, Any
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  1. RiscvCoreConfig
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Instance Constructors

  1. new RiscvCoreConfig(pcWidth: Int = 32, addrWidth: Int = 32, startAddress: Int = 0, bypassExecute0: Boolean = true, bypassExecute1: Boolean = true, bypassWriteBack: Boolean = true, bypassWriteBackBuffer: Boolean = true, collapseBubble: Boolean = true, branchPrediction: BranchPrediction = static, regFileReadyKind: RegFileReadKind = sync, fastFetchCmdPcCalculation: Boolean = true, dynamicBranchPredictorCacheSizeLog2: Int = 4, branchPredictorHistoryWidth: Int = 2, invalidInstructionIrqId: Int = 0, unalignedMemoryAccessIrqId: Int = 1)

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Value Members

  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. def add[T <: CoreExtension](that: T): T

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  5. val addrWidth: Int

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  6. final def asInstanceOf[T0]: T0

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  7. val branchPrediction: BranchPrediction

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  8. val branchPredictorHistoryWidth: Int

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  9. val bypassExecute0: Boolean

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  10. val bypassExecute1: Boolean

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  11. val bypassWriteBack: Boolean

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  12. val bypassWriteBackBuffer: Boolean

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  13. def clone(): AnyRef

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    protected[java.lang]
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  14. val collapseBubble: Boolean

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  15. val dynamicBranchPredictorCacheSizeLog2: Int

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  16. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
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  17. val extensions: ArrayBuffer[CoreExtension]

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  18. val fastFetchCmdPcCalculation: Boolean

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  19. def finalize(): Unit

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  20. final def getClass(): Class[_]

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  21. val invalidInstructionIrqId: Int

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  22. final def isInstanceOf[T0]: Boolean

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  23. final def ne(arg0: AnyRef): Boolean

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  24. def needExecute0PcPlus4: Boolean

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  25. final def notify(): Unit

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  26. final def notifyAll(): Unit

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  27. val pcWidth: Int

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  28. val regFileReadyKind: RegFileReadKind

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  29. val startAddress: Int

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  30. final def synchronized[T0](arg0: ⇒ T0): T0

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  31. val unalignedMemoryAccessIrqId: Int

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  32. final def wait(): Unit

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  33. final def wait(arg0: Long, arg1: Int): Unit

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  34. final def wait(arg0: Long): Unit

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Inherited from Serializable

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Inherited from Product

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