lib

Type Members

class AnyPimped[T] extends AnyRef
implicit class BigIntRicher extends LiteralRicher
implicit class BinIntsRicher extends AnyRef
implicit class BinaryBuilder extends AnyRef
implicit class BinaryBuilder2 extends AnyRef
class BitAggregator extends AnyRef
class BoolPimped extends AnyRef
class BufferCC[T <: Data] extends Component
implicit class ByteRicher extends LiteralRicher
class ClockDomainPimped extends AnyRef
class Counter extends ImplicitArea[UInt]
class CounterUpDown extends ImplicitArea[UInt]
trait DataCarrier[T <: Data] extends AnyRef
class DataCarrierFragmentBitsPimped extends AnyRef
class DataCarrierFragmentPimped[T <: Data] extends AnyRef
case class DataOr[T <: Data](dataType: HardType[T]) extends Area with Product with Serializable
type Event = Stream[NoData]
case class EventEmitter(on: Event) extends Product with Serializable
class EventFactory extends MSFactory
class Flow[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]
class FlowBitsPimped extends AnyRef
class FlowCCByToggle[T <: Data] extends Component
class FlowCmdRsp[T <: Data, T2 <: Data] extends Bundle with IMasterSlave
class FlowFactory extends MSFactory
class FlowFragmentBitsRouter extends AnyRef
class FlowFragmentFactory extends MSFactory
class FlowFragmentPimped[T <: Data] extends AnyRef
class Fragment[T <: Data] extends Bundle
class FragmentFactory extends AnyRef
class GrowableAnyPimped[T] extends AnyRef
class HistoryModifyable[T <: Data] extends Component
trait IMasterSlave extends AnyRef

Master/slave interface
implicit class IntRicher extends LiteralRicher
trait LiteralRicher extends AnyRef
implicit class LongRicher extends LiteralRicher
sealed trait MS extends AnyRef

Declare a port as master or slave
Declare a port as master or slave
There are 4 available syntaxes, which are all equivalent:
```
val braces = master(Flow(Bool))

val short = master Flow (Bool)

val spaceful = master port Flow(Bool)

val variadic = Flow(Bool)
master(variadic)
```
The "braces" syntax is short and generic, but it uses braces.
The "short" syntax is short, but it is formatted with a space between the type and its parameters, and it can be used only with:
- Flow
- Stream
The "spaceful" syntax is generic and beatiful, but more verbose.
The "variadic" syntax can be used with any number of interfaces, but can be used only if the interfaces are already declared.
See also
master slave
trait MSFactory extends AnyRef

Something which can create master/slave interfaces
class MemPimped[T <: Data] extends AnyRef
case class MemReadPort[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable
case class MemReadPortAsync[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable
case class MemReadWritePort[T <: Data](dataType: T, addressWidth: Int, maskWidth: Int = 1) extends Bundle with IMasterSlave with Product with Serializable
case class MemWriteCmd[T <: Data](mem: Mem[T], maskWidth: Int = 1) extends Bundle with Product with Serializable
case class MemWriteCmdWithMask[T <: Data](mem: Mem[T], maskWidth: Int) extends Bundle with Product with Serializable
class MuxOHImpl extends AnyRef
class NoData extends Bundle
class PackedBundle extends Bundle

Similar to Bundle but with bit packing capabilities.
Similar to Bundle but with bit packing capabilities. Use pack implicit functions to assign fields to bit locations - pack(Range, [Endianness]) - Packs the data into Range aligning to bit Endianness if too wide - packFrom(Position) - Packs the data starting (LSB) at Position. Uses full data length - packTo(Position) - Packs the data ending (MSB) at Position. Uses full data length
Providing no location tag will place the next data value immediately after the last.
Example:
1. val regWord = new PackedBundle { val init = Bool().packFrom(0) // Bit 0 val stop = Bool() // Bit 1 val result = Bits(16 bit).packTo(31) // Bits 16 to 31 }
class PackedWordBundle extends PackedBundle

An enhanced form of PackedBundle with Word-centric packing.
An enhanced form of PackedBundle with Word-centric packing. Offers all the same implicit packing assignment functions, but applies packing to an assigned word. - inWord(WordIndex) - Indicates which word to pack into. Must be used after a pack assigment. If no pack range was given then the entire data length will be assumed. Ranges that exceed the word will wrap into subsequent words.
Like PackedBundle, providing no pack or word assignments will place data immediately after the last.
Example:
1. val wordPacked = PackedWordBundle(8 bits) { val aNumber = UInt(8 bits).word(0) // Bits 7 downto 0 val bNumber = UInt(8 bits).pack(0 to 7).word(1) // Bits 8 to 15 val large = Bits(18 bits).word(2) // Bits 33 downto 16 val flag = Bool() // Bit 34
class PulseCCByToggle extends Component
case class ReadRetLinked[T <: Data, T2 <: Data](readType: HardType[T], linkedType: HardType[T2]) extends Bundle with Product with Serializable
type ScalaStream[T] = scala.collection.immutable.Stream[T]
sealed trait SlicesOrder extends AnyRef

Enumeration to present order of slices.
class Stream[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]
class StreamArbiter[T <: Data] extends Component

A StreamArbiter is like a StreamMux, but with built-in complex selection logic that can arbitrate input streams based on a schedule or handle fragmented streams.
A StreamArbiter is like a StreamMux, but with built-in complex selection logic that can arbitrate input streams based on a schedule or handle fragmented streams. Use a StreamArbiterFactory to create instances of this class.
class StreamArbiterFactory extends AnyRef
class StreamBitsPimped extends AnyRef
class StreamBundlePimped[T <: Bundle] extends AnyRef
class StreamCCByToggle[T <: Data] extends Component
class StreamDemux[T <: Data] extends Component
class StreamFactory extends MSFactory
class StreamFifo[T <: Data] extends Component

Fully redesigned in release 1.8.2 allowing improved timing closure.
Fully redesigned in release 1.8.2 allowing improved timing closure. - latency of 0, 1, 2 cycles
class StreamFifoCC[T <: Data] extends Component
trait StreamFifoInterface[T <: Data] extends AnyRef
class StreamFifoLowLatency[T <: Data] extends Component
case class StreamFifoMultiChannelPop[T <: Data](payloadType: HardType[T], channelCount: Int) extends Bundle with IMasterSlave with Product with Serializable
case class StreamFifoMultiChannelPush[T <: Data](payloadType: HardType[T], channelCount: Int) extends Bundle with IMasterSlave with Product with Serializable
case class StreamFifoMultiChannelSharedSpace[T <: Data](payloadType: HardType[T], channelCount: Int, depth: Int, withAllocationFifo: Boolean = false) extends Component with Product with Serializable
class StreamFlowArbiter[T <: Data] extends Area
class StreamFork[T <: Data] extends Component

A StreamFork will clone each incoming data to all its output streams.
A StreamFork will clone each incoming data to all its output streams. If synchronous is true, all output streams will always fire together, which means that the stream will halt until all output streams are ready. If synchronous is false, output streams may be ready one at a time, at the cost of an additional flip flop (1 bit per output). The input stream will block until all output streams have processed each item regardlessly.
Note that this means that when synchronous is true, the valid signal of the outputs depends on their inputs, which may lead to dead locks when used in combination with systems that have it the other way around. It also violates the handshake of the AXI specification (section A3.3.1).
class StreamForkArea[T <: Data] extends Area
class StreamFragmentBitsDispatcher extends Area
case class StreamFragmentBitsDispatcherElement(sink: Stream[Bits], header: Int) extends Product with Serializable
class StreamFragmentBitsPimped extends AnyRef
class StreamFragmentFactory extends MSFactory
class StreamFragmentPimped[T <: Data] extends AnyRef
class StreamMux[T <: Data] extends Component
class StreamPacker[T <: Data] extends Area

Packs layout's Data into the given stream
Packs layout's Data into the given stream
stream is directly driven by this area.
layout Data is read directly
io.start indicates when to start packing. All layout's Data is registered before packing.
io.done indicates when the last word has been packed.
Use the companion object StreamPapcker to create an instance.
trait StreamPipe extends AnyRef
class StreamToStreamFragmentBits[T <: Data] extends Component
class StreamTransactionCounter extends Component
class StreamTransactionExtender[T <: Data, T2 <: Data] extends Component
class StreamUnpacker[T <: Data] extends Area

Unpacks stream's words into the given layout's Data.
Unpacks stream's words into the given layout's Data. stream is directly driven by this area. layout Data are driven through a register.
io.start starts unpacking io.dones is set of bits indicating when the associated Data in layout is unpacked. io.allDone indicates when the last word has been unpacked.
Use the companion object StreamUnpacker to create an instance.
class StringPimped extends AnyRef
class Timeout extends ImplicitArea[Bool]
class TraversableOnceAddressTransformerPimped extends AnyRef
class TraversableOnceAnyPimped[T] extends AnyRef
class TraversableOnceAnyTuplePimped[T, T2] extends AnyRef
class TraversableOnceBoolPimped extends AnyRef
class TraversableOncePimped[T <: Data] extends AnyRef
implicit class UIntPimper extends AnyRef
case class WhenBuilder() extends Product with Serializable
class StreamDispatcherSequencial[T <: Data] extends Component

Deprecated
Do not use. Use the companion object or a normal regular StreamMux instead.

Value Members

object AddWithCarry
object AnalysisUtils
implicit def AnyPimpedDef[T](that: T): AnyPimped[T]
object BufferCC
object Callable
object ClearCount
object CountOne
object CountOneOnEach
object Counter

Creates a counter
Creates a counter
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/utils.html?highlight=counter#counter
object CounterFreeRun

Creates an always running counter
Creates an always running counter
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/utils.html?highlight=counter#counter
object CounterMultiRequest
object CounterUpDown
object DataCarrier
object Delay
object DelayEvent
object DelayWithInit
object DoCmd

Run command
object EndiannessSwap

**************************************************************************** Big-Endian <-> Little-Endian
def Event: Stream[NoData]
object Flow extends FlowFactory
object FlowCCByToggle
object FlowCmdRsp
object FlowFragmentBitsRouter
object Fragment extends FragmentFactory
object FragmentToBitsStates extends SpinalEnum
object GrayCounter
object HIGHER_FIRST extends SlicesOrder

Slice with higher bits process first
object History
object HistoryModifyable
object KeepAttribute
object LOWER_FIRST extends SlicesOrder

Slice with lower bits process first
object LatencyAnalysis
object LeastSignificantBitSet
object MajorityVote
object Max
object Min
object MuxOH extends MuxOHImpl
def NoData(): NoData
object OHMasking
val OHMux: MuxOHImpl
object OHToUInt
object OhMux extends MuxOHImpl
object PriorityMux
object PulseCCByToggle
object RegFlow
object Repeat
object ResetCtrl
object Reverse
def ScalaStream: scala.collection.immutable.Stream.type
object SetCount
object SetFromFirstOne
object Shift
object Stream extends StreamFactory
object StreamArbiter
def StreamArbiterFactory(): StreamArbiterFactory
object StreamCCByToggle
object StreamCombinerSequential

This is equivalent to a StreamMux, but with a counter attached to the port selector.
object StreamDemux

Demultiplex one stream into multiple output streams, always selecting only one at a time.
object StreamDemuxOh
object StreamDispatcherSequential

This is equivalent to a StreamDemux, but with a counter attached to the port selector.
object StreamFifo
object StreamFifoCC
object StreamFifoLowLatency
object StreamFifoMultiChannelBench extends App
object StreamFlowArbiter

Combine a stream and a flow to a new stream.
Combine a stream and a flow to a new stream. If both input sources fire, the flow will be preferred.
object StreamFork
object StreamFork2
object StreamFork3
object StreamFragmentArbiter
object StreamFragmentArbiterAndHeaderAdder
object StreamFragmentGenerator
object StreamFragmentWidthAdapter
object StreamJoin

Join multiple streams into one.
Join multiple streams into one. The resulting stream will only fire if all of them fire, so you may want to buffer the inputs.
object StreamMux

Multiplex multiple streams into a single one, always only processing one at a time.
object StreamPacker
object StreamPipe
object StreamTransactionCounter
object StreamTransactionExtender
object StreamUnpacker
object StreamWidthAdapter
object Timeout
object UIntToOh
object ValidFlow

Create a new Flow that is always valid, with a given payload
object WrapWithReg
package blackbox
implicit def boolPimped(that: Bool): BoolPimped
package bus
implicit def clockDomainPimped(cd: ClockDomain): ClockDomainPimped
package com
package cpu
implicit def dataCarrierFragmentBitsPimped(that: DataCarrier[Fragment[Bits]]): DataCarrierFragmentBitsPimped
implicit def dataCarrierFragmentPimped[T <: Data](that: DataCarrier[Fragment[T]]): DataCarrierFragmentPimped[T]
package dsptool
implicit def easyFragment[T <: Data](that: Fragment[T]): T
package eda
package experimental
implicit def flowBitsPimped(that: Flow[Bits]): FlowBitsPimped
implicit def flowFragmentPimped[T <: Data](that: Flow[Fragment[T]]): FlowFragmentPimped[T]
package formal
object fromGray
package fsm
package generator
package generator_backup
package graphic
implicit def growableAnyPimped[T](that: Growable[T]): GrowableAnyPimped[T]
package io
package logic
object master extends MS

Declare a master port
Declare a master port
See MS for syntax help.
package math
implicit def memPimped[T <: Data](mem: Mem[T]): MemPimped[T]
package memory
package misc
package pipeline
def sexport[T <: SpinalTag](h: T): T
def sexport[T](name: String, value: Any): ArrayBuffer[() ⇒ Unit]
def sexport[T](h: Handle[T]): Handle[T]
def sexport[T](named: Handle[T], value: ⇒ Any): ArrayBuffer[() ⇒ Unit]
package sim
object slave extends MS

Declare a slave port
Declare a slave port
See MS for syntax help.
package soc
implicit def streamBitsPimped(that: Stream[Bits]): StreamBitsPimped
implicit def streamBundlePimped[T <: Bundle](that: Stream[T]): StreamBundlePimped[T]
implicit def streamFragmentBitsPimped(that: Stream[Fragment[Bits]]): StreamFragmentBitsPimped
implicit def streamFragmentPimped[T <: Data](that: Stream[Fragment[T]]): StreamFragmentPimped[T]
implicit def stringPimped(that: String): StringPimped
package system
object toGray
package tools
implicit def traversableOnceAddressTransformerPimped(that: TraversableOnce[AddressTransformer]): TraversableOnceAddressTransformerPimped
implicit def traversableOnceAnyPimped[T](that: TraversableOnce[T]): TraversableOnceAnyPimped[T]
implicit def traversableOnceAnyTuplePimped[T, T2](that: TraversableOnce[(T, T2)]): TraversableOnceAnyTuplePimped[T, T2]
implicit def traversableOnceBoolPimped(that: TraversableOnce[Bool]): TraversableOnceBoolPimped
implicit def traversableOncePimped[T <: Data](that: TraversableOnce[T]): TraversableOncePimped[T]
object whenIndexed
object whenMasked
package wishbone

Deprecated Value Members

object StreamDispatcherSequencial

Deprecated
Do not use
object masterWithNull extends MS

Annotations
@deprecated
Deprecated
Use apply or port instead: 'val b = master(maybeNull)' or 'val rgb = master port maybeNull'
object slaveWithNull extends MS

Annotations
@deprecated
Deprecated
Use apply or port instead: 'val b = slave(maybeNull)' or 'val rgb = slave port maybeNull'

package lib

Type Members

class AnyPimped[T] extends AnyRef

implicit class BigIntRicher extends LiteralRicher

implicit class BinIntsRicher extends AnyRef

implicit class BinaryBuilder extends AnyRef

implicit class BinaryBuilder2 extends AnyRef

class BitAggregator extends AnyRef

class BoolPimped extends AnyRef

class BufferCC[T <: Data] extends Component

implicit class ByteRicher extends LiteralRicher

class ClockDomainPimped extends AnyRef

class Counter extends ImplicitArea[UInt]

class CounterUpDown extends ImplicitArea[UInt]

trait DataCarrier[T <: Data] extends AnyRef

class DataCarrierFragmentBitsPimped extends AnyRef

class DataCarrierFragmentPimped[T <: Data] extends AnyRef

case class DataOr[T <: Data](dataType: HardType[T]) extends Area with Product with Serializable

type Event = Stream[NoData]

case class EventEmitter(on: Event) extends Product with Serializable

class EventFactory extends MSFactory

class Flow[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]

class FlowBitsPimped extends AnyRef

class FlowCCByToggle[T <: Data] extends Component

class FlowCmdRsp[T <: Data, T2 <: Data] extends Bundle with IMasterSlave

class FlowFactory extends MSFactory

class FlowFragmentBitsRouter extends AnyRef

class FlowFragmentFactory extends MSFactory

class FlowFragmentPimped[T <: Data] extends AnyRef

class Fragment[T <: Data] extends Bundle

class FragmentFactory extends AnyRef

class GrowableAnyPimped[T] extends AnyRef

class HistoryModifyable[T <: Data] extends Component

trait IMasterSlave extends AnyRef

implicit class IntRicher extends LiteralRicher

trait LiteralRicher extends AnyRef

implicit class LongRicher extends LiteralRicher

sealed trait MS extends AnyRef

trait MSFactory extends AnyRef

class MemPimped[T <: Data] extends AnyRef

case class MemReadPort[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable

case class MemReadPortAsync[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable

case class MemReadWritePort[T <: Data](dataType: T, addressWidth: Int, maskWidth: Int = 1) extends Bundle with IMasterSlave with Product with Serializable

case class MemWriteCmd[T <: Data](mem: Mem[T], maskWidth: Int = 1) extends Bundle with Product with Serializable

case class MemWriteCmdWithMask[T <: Data](mem: Mem[T], maskWidth: Int) extends Bundle with Product with Serializable

class MuxOHImpl extends AnyRef

class NoData extends Bundle

class PackedBundle extends Bundle

class PackedWordBundle extends PackedBundle

class PulseCCByToggle extends Component

case class ReadRetLinked[T <: Data, T2 <: Data](readType: HardType[T], linkedType: HardType[T2]) extends Bundle with Product with Serializable

type ScalaStream[T] = scala.collection.immutable.Stream[T]

sealed trait SlicesOrder extends AnyRef

class Stream[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]

class StreamArbiter[T <: Data] extends Component

class StreamArbiterFactory extends AnyRef

class StreamBitsPimped extends AnyRef

class StreamBundlePimped[T <: Bundle] extends AnyRef

class StreamCCByToggle[T <: Data] extends Component

class StreamDemux[T <: Data] extends Component

class StreamFactory extends MSFactory

class StreamFifo[T <: Data] extends Component

class StreamFifoCC[T <: Data] extends Component

trait StreamFifoInterface[T <: Data] extends AnyRef

class StreamFifoLowLatency[T <: Data] extends Component

case class StreamFifoMultiChannelPop[T <: Data](payloadType: HardType[T], channelCount: Int) extends Bundle with IMasterSlave with Product with Serializable

case class StreamFifoMultiChannelPush[T <: Data](payloadType: HardType[T], channelCount: Int) extends Bundle with IMasterSlave with Product with Serializable

case class StreamFifoMultiChannelSharedSpace[T <: Data](payloadType: HardType[T], channelCount: Int, depth: Int, withAllocationFifo: Boolean = false) extends Component with Product with Serializable

class StreamFlowArbiter[T <: Data] extends Area

class StreamFork[T <: Data] extends Component

class StreamForkArea[T <: Data] extends Area

class StreamFragmentBitsDispatcher extends Area

case class StreamFragmentBitsDispatcherElement(sink: Stream[Bits], header: Int) extends Product with Serializable

class StreamFragmentBitsPimped extends AnyRef

class StreamFragmentFactory extends MSFactory

class StreamFragmentPimped[T <: Data] extends AnyRef

class StreamMux[T <: Data] extends Component

class StreamPacker[T <: Data] extends Area

trait StreamPipe extends AnyRef