de.sciss.synth.ugen

Gate

Related Docs: class Gate | package ugen

object Gate extends Serializable

A gate or hold UGen. It allows the input signal value to pass when the gate argument is positive, otherwise it holds last value.

See also

Latch

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  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. def ar(in: GE, gate: GE): Gate

    in

    the input signal to gate

    gate

    the signal specifying whether to pass the input signal (when greater than zero) or whether to close the gate and hold the last value (when less than or equal to zero)

  5. final def asInstanceOf[T0]: T0

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  6. def clone(): AnyRef

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  11. def hashCode(): Int

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  12. final def isInstanceOf[T0]: Boolean

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  13. def kr(in: GE, gate: GE): Gate

    in

    the input signal to gate

    gate

    the signal specifying whether to pass the input signal (when greater than zero) or whether to close the gate and hold the last value (when less than or equal to zero)

  14. final def ne(arg0: AnyRef): Boolean

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  15. final def notify(): Unit

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  16. final def notifyAll(): Unit

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  17. final def synchronized[T0](arg0: ⇒ T0): T0

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