OrderedDecoupledHWIOTester

Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated

Example:

```
class XTimesXTester extends [[OrderedDecoupledHWIOTester]] {
  val device_under_test = new XTimesY
  test_block {
    for {
      i <- 0 to 10
      j <- 0 to 10
    } {
      input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j)
      output_event(device_under_test.io.out.z -> i*j)
    }
  }
}
```
an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created

Linear Supertypes

HWIOTester, BasicTester, Module, HasId, AnyRef, Any

Instance Constructors

new OrderedDecoupledHWIOTester()

Type Members

class GlobalEventCounter extends AnyRef
case class TestingEvent(port_values: Map[Data, Int], event_number: Int) extends Product with Serializable

Abstract Value Members

abstract val device_under_test: Module

Definition Classes
HWIOTester

Concrete Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def asInstanceOf[T0]: T0

Definition Classes
Any
def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, Int)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes
val clock: Clock

Definition Classes
Module
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
var enable_all_debug: Boolean

Definition Classes
HWIOTester
var enable_printf_debug: Boolean

Definition Classes
HWIOTester
var enable_scala_debug: Boolean

Definition Classes
HWIOTester
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def finish(): Unit

this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid
this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

Definition Classes
OrderedDecoupledHWIOTester → HWIOTester → BasicTester
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommonValidParentPort(expects: Seq[(Data, Int)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes
def hashCode(): Int

Definition Classes
AnyRef → Any
def inputEvent(pokes: (Data, Int)*): Unit
val input_event_list: ArrayBuffer[Seq[(Data, Int)]]
val io: Bundle

Definition Classes
BasicTester → Module
var io_info: IOAccessor

Definition Classes
HWIOTester
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def logPrintfDebug(fmt: String, args: Bits*): Unit

Definition Classes
HWIOTester
def logScalaDebug(msg: ⇒ String): Unit

Definition Classes
HWIOTester
val name: String

Definition Classes
Module
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
def outputEvent(expects: (Data, Int)*): Unit
val output_event_list: ArrayBuffer[Seq[(Data, Int)]]
def popCount(n: Long): Int

Definition Classes
BasicTester
val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]
val port_to_valid: HashMap[Data, ValidIO[Data]]
def processInputEvents(): Unit

iterate over recorded events, checking constraints on ports referenced, etc.
iterate over recorded events, checking constraints on ports referenced, etc. use poke and expect to record
def processOutputEvents(): Unit
val reset: Bool

Definition Classes
Module
val rnd: Random.type

Definition Classes
HWIOTester
def stop(): Unit

Definition Classes
BasicTester
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Docs: object OrderedDecoupledHWIOTester | package hwiotesters

abstract class OrderedDecoupledHWIOTester extends HWIOTester

Instance Constructors

new OrderedDecoupledHWIOTester()

Type Members

class GlobalEventCounter extends AnyRef

case class TestingEvent(port_values: Map[Data, Int], event_number: Int) extends Product with Serializable

Abstract Value Members

abstract val device_under_test: Module

Concrete Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, Int)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

val clock: Clock

def clone(): AnyRef

val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]

val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]

var enable_all_debug: Boolean

var enable_printf_debug: Boolean

var enable_scala_debug: Boolean

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

def finish(): Unit

final def getClass(): Class[_]

def getCommonValidParentPort(expects: Seq[(Data, Int)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

def hashCode(): Int

def inputEvent(pokes: (Data, Int)*): Unit

val input_event_list: ArrayBuffer[Seq[(Data, Int)]]

val io: Bundle

var io_info: IOAccessor

final def isInstanceOf[T0]: Boolean

def logPrintfDebug(fmt: String, args: Bits*): Unit

def logScalaDebug(msg: ⇒ String): Unit

val name: String

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def outputEvent(expects: (Data, Int)*): Unit

val output_event_list: ArrayBuffer[Seq[(Data, Int)]]

def popCount(n: Long): Int

val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]

val port_to_valid: HashMap[Data, ValidIO[Data]]

def processInputEvents(): Unit

def processOutputEvents(): Unit

val reset: Bool

val rnd: Random.type

def stop(): Unit

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from HWIOTester

Inherited from BasicTester

Inherited from Module

Inherited from HasId

Inherited from AnyRef

Inherited from Any

Ungrouped