OrderedDecoupledHWIOTester

abstract val device_under_test: Module

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: core.Data](iodef: T): T

def _bindIoInPlace(iodef: core.Data): Unit

var _closed: Boolean

def _compatAutoWrapPorts(): Unit

def _compatIoPortBound(): Boolean

final def asInstanceOf[T0]: T0

def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, BigInt)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes

def circuitName: String

val clock: core.Clock

def clone(): AnyRef

val compileOptions: CompileOptions

val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]

val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]

def desiredName: String

var enable_all_debug: Boolean

var enable_printf_debug: Boolean

var enable_scala_debug: Boolean

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

def finish(): Unit

this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getCommonValidParentPort(expects: Seq[(Data, BigInt)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes

def getIds: Seq[HasId]

def getModulePorts: Seq[core.Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def inputEvent(pokes: (Data, BigInt)*): Unit

val input_event_list: ArrayBuffer[Seq[(Data, BigInt)]]

def instanceName: String

val io: Bundle

var io_info: IOAccessor

final def isInstanceOf[T0]: Boolean

def logPrintfDebug(fmt: String, args: Bits*): Unit

def logScalaDebug(msg: ⇒ String): Unit

final val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def outputEvent(expects: (Data, BigInt)*): Unit

val output_event_list: ArrayBuffer[Seq[(Data, BigInt)]]

var override_clock: Option[core.Clock]

var override_reset: Option[core.Bool]

def parentModName: String

def parentPathName: String

def pathName: String

def popCount(n: Long): Int

val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]

val port_to_valid: HashMap[Data, ValidIO[Data]]

def portsContains(elem: core.Data): Boolean

def portsSize: Int

def processInputEvents(): Unit

iterate over recorded events, checking constraints on ports referenced, etc.

def processOutputEvents(): Unit

val reset: Reset

val rnd: Random.type

def stop()(implicit sourceInfo: SourceInfo): Unit

def suggestName(name: ⇒ String): OrderedDecoupledHWIOTester.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

final def toNamed: ModuleName

def toString(): String

val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def annotate(annotation: ChiselAnnotation): Unit