VcsExecutive

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

def clone(): AnyRef

def combinationalPathsToData(dut: BaseModule, paths: Seq[CombinationalPath], dataNames: Map[Data, String], componentToName: (ReferenceTarget) ⇒ String): Map[Data, Set[Data]]

This creates some kind of map of combinational paths between inputs and outputs.

def componentToName(component: ReferenceTarget): String

Verilator wants to have module name prefix except for default reset and clock

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

final def getClass(): Class[_]

def getDataNames(name: String, data: Data): Seq[(Data, String)]

Returns a Seq of (data reference, fully qualified element names) for the input.

def getTopModule(circuit: Circuit): BaseModule

def hashCode(): Int

final def isInstanceOf[T0]: Boolean

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def start[T <: MultiIOModule](dutGen: () ⇒ T, annotationSeq: AnnotationSeq): BackendInstance[T]

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit