Vec
Related Doc:
package chisel3
Strong bulk connect, assigning elements in this Vec from elements in a Seq.
Strong bulk connect, assigning elements in this Vec from elements in a Seq.
the length of this Vec must match the length of the input Seq
Connect this data to that data mono-directionally and element-wise.
Connect this data to that data mono-directionally and element-wise.
This uses the MonoConnect algorithm.
the data to connect to
Strong bulk connect, assigning elements in this Vec from elements in a Seq.
Strong bulk connect, assigning elements in this Vec from elements in a Seq.
the length of this Vec must match the length of the input Seq
Connect this data to that data bi-directionally and element-wise.
Connect this data to that data bi-directionally and element-wise.
This uses the BiConnect algorithm.
the data to connect to
Creates a statically indexed read or write accessor into the array.
Creates a statically indexed read or write accessor into the array.
Creates a dynamically indexed read or write accessor into the array.
Does a reinterpret cast of the bits in this node into the format that provides.
Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.
x.asTypeOf(that) performs the inverse operation of x := that.toBits.
that should have known widths
,bit widths are NOT checked, may pad or drop bits from input
Reinterpret cast to UInt.
Reinterpret cast to UInt.
Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.
,value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7
Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
Outputs true if the vector contains at least one element equal to x (using the === operator).
Outputs true if the vector contains at least one element equal to x (using the === operator).
Outputs the number of elements for which p is true.
Outputs the number of elements for which p is true.
Outputs true if p outputs true for at least one element.
Outputs true if p outputs true for at least one element.
Outputs true if p outputs true for every element.
Outputs true if p outputs true for every element.
Returns a Seq of the immediate contents of this Aggregate, in order.
Returns the width, in bits, if currently known.
Returns the width, in bits, if currently known.
Outputs the index of the first element for which p outputs true.
Outputs the index of the first element for which p outputs true.
Returns whether the width is currently known.
Returns whether the width is currently known.
Outputs the index of the last element for which p outputs true.
Outputs the index of the last element for which p outputs true.
If this is a literal that is representable as bits, returns the value as a BigInt.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Outputs the index of the element for which p outputs true, assuming that the there is exactly one such element.
Outputs the index of the element for which p outputs true, assuming that the there is exactly one such element.
The implementation may be more efficient than a priority mux, but incorrect results are possible if there is not exactly one true element.
the assumption that there is only one element for which p outputs true is NOT checked (useful in cases where the condition doesn't always hold, but the results are not used in those cases)
A reduce operation in a tree like structure instead of sequentially
A reduce operation in a tree like structure instead of sequentially
A pipelined adder tree
val sumOut = inputNums.reduceTree( (a: T, b: T) => RegNext(a + b), (a: T) => RegNext(a) )
A reduce operation in a tree like structure instead of sequentially
A reduce operation in a tree like structure instead of sequentially
An adder tree
val sumOut = inputNums.reduceTree((a: T, b: T) => (a + b))
(Changed in version 2.9.0) The behavior of scanRight has changed. The previous behavior can be reproduced with scanRight.reverse.
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
Should not be called until circuit elaboration is complete
Default "pretty-print" implementation Analogous to printing a Seq Results in "Vec(elt0, elt1, ...)"
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
Should not be called until circuit elaboration is complete
(Changed in version 2.9.0) transpose throws an IllegalArgumentException if collections are not uniformly sized.
Returns Some(width) if the width is known, else None.
Returns Some(width) if the width is known, else None.
(Since version ) see corresponding Javadoc for more information.
(Since version 3.2) litArg is deprecated, use litOption or litTo*Option
Utilities for connecting hardware components
A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.
Careful consideration should be given over the use of Vec vs Seq or some other Scala collection. In general Vec only needs to be used when there is a need to express the hardware collection in a Reg or IO Bundle or when access to elements of the array is indexed via a hardware signal.
Example of indexing into a Vec using a hardware address and where the Vec is defined in an IO Bundle
type of elements