abstract class VerificationStatement extends NamedComponent
Base class for all verification statements: Assert, Assume, Cover, Stop and Printf.
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- new VerificationStatement()
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- final def !=(arg0: Any): Boolean
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- def circuitName: String
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- def hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
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- def hashCode(): Int
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- def instanceName: String
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- def parentModName: String
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- def parentPathName: String
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- def pathName: String
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- def suggestName(seed: => String): VerificationStatement.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
- seed
The seed for the name of this component
- returns
this object
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- final def synchronized[T0](arg0: => T0): T0
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- final def toAbsoluteTarget: ReferenceTarget
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
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- final def toNamed: ComponentName
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
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- Note
Should not be called until circuit elaboration is complete
- def toString(): String
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- final def toTarget: ReferenceTarget
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
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Should not be called until circuit elaboration is complete
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