object
Pipe
Value Members
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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def
apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T]
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def
apply[T <: Data](enq: Valid[T], latency: Int = 1)(implicit compileOptions: CompileOptions): Valid[T]
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def
apply[T <: Data](enqValid: Bool, enqBits: T)(implicit compileOptions: CompileOptions): Valid[T]
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final
def
asInstanceOf[T0]: T0
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def
clone(): AnyRef
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def
finalize(): Unit
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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final
def
isInstanceOf[T0]: Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter. Functionality is similar to ShiftRegister but this exposes a Pipe interface.
Example usage: val pipe = new Pipe(UInt()) pipe.io.enq <> produce.io.out consumer.io.in <> pipe.io.deq