ChiselStage

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

def clone(): AnyRef

final def emitChirrtl(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

Convert a Chisel module to a CHIRRTL string

final def emitFirrtl(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

Convert a Chisel module to a FIRRTL string

final def emitSystemVerilog(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

Convert a Chisel module to SystemVerilog

final def emitVerilog(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

Convert a Chisel module to Verilog

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

final def execute(args: Array[String], annotations: AnnotationSeq): AnnotationSeq

def finalize(): Unit

final def getClass(): Class[_]

def hashCode(): Int

def invalidates(a: Phase): Boolean

final def isInstanceOf[T0]: Boolean

val logger: Logger

lazy val name: String

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def optionalPrerequisiteOf: Seq[Nothing]

def optionalPrerequisites: Seq[Nothing]

final lazy val phaseManager: ChiselPhase

def prerequisites: Seq[Nothing]

def run(annotations: AnnotationSeq): AnnotationSeq

val shell: Shell

final def synchronized[T0](arg0: ⇒ T0): T0

val targets: Seq[PhaseDependency]

def toString(): String

final def transform(annotations: AnnotationSeq): AnnotationSeq

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def dependents: Seq[Dependency[Phase]]