Module

Value Members

final def !=(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def !=(arg0: Any): Boolean

Definition Classes
Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def ==(arg0: Any): Boolean

Definition Classes
Any
def apply[T <: Module](c: ⇒ T): T
final def asInstanceOf[T0]: T0

Definition Classes
Any
var backend: Backend
var chiselAndMap: HashMap[(Node, Node), Bool]
var chiselOneHotBitMap: HashMap[(Bits, Int), Bool]
var chiselOneHotMap: HashMap[(UInt, Int), UInt]
val clocks: ArrayBuffer[Clock]
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compStack: Stack[Module]
val components: ArrayBuffer[Module]
var dontFindCombLoop: Boolean
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getComponent(): Module
def hashCode(): Int

Definition Classes
AnyRef → Any
var implicitClock: Clock
var implicitReset: Bool
var includeArgs: List[String]
def initChisel(): Unit
var ioCount: Int
var ioMap: HashMap[Node, Int]
var isCheckingPorts: Boolean
var isClockGatingUpdates: Boolean
var isClockGatingUpdatesInline: Boolean
var isCompiling: Boolean
var isDebug: Boolean
var isEmittingComponents: Boolean
var isFolding: Boolean
var isGenHarness: Boolean
var isInlineMem: Boolean
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
var isIoDebug: Boolean
var isPruning: Boolean
var isReportDims: Boolean
def isSubclassOfModule(x: Class[_]): Boolean
var isTesting: Boolean
var isVCD: Boolean
val keywords: HashSet[String]
val muxes: ArrayBuffer[Node]
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val nodes: ArrayBuffer[Node]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
def pop(): Unit
var printArgs: ArrayBuffer[Node]
var printFormat: String
var printStackStruct: ArrayBuffer[(Int, Module)]
val printfs: ArrayBuffer[Printf]
val procs: ArrayBuffer[proc]
val randInitIOs: ArrayBuffer[Node]
val resetList: ArrayBuffer[Node]
var saveComponentTrace: Boolean
var saveConnectionWarnings: Boolean
var saveWidthWarnings: Boolean
var scanArgs: ArrayBuffer[Node]
var scanFormat: String
var searchAndMap: Boolean
def setAsTopComponent(mod: Module): Unit
var sortedComps: ArrayBuffer[Module]
def splitArg(s: String): List[String]
var stackIndent: Int
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
var targetDir: String
var tester: Tester[Module]
def toString(): String

Definition Classes
AnyRef → Any
var topComponent: Module
var trigger: Boolean
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
var warnInputs: Boolean
var warnOutputs: Boolean

object Module

Value Members

final def !=(arg0: AnyRef): Boolean

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: AnyRef): Boolean

final def ==(arg0: Any): Boolean

def apply[T <: Module](c: ⇒ T): T

final def asInstanceOf[T0]: T0

var backend: Backend

var chiselAndMap: HashMap[(Node, Node), Bool]

var chiselOneHotBitMap: HashMap[(Bits, Int), Bool]

var chiselOneHotMap: HashMap[(UInt, Int), UInt]

val clocks: ArrayBuffer[Clock]

def clone(): AnyRef

val compStack: Stack[Module]

val components: ArrayBuffer[Module]

var dontFindCombLoop: Boolean

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getComponent(): Module

def hashCode(): Int

var implicitClock: Clock

var implicitReset: Bool

var includeArgs: List[String]

def initChisel(): Unit

var ioCount: Int

var ioMap: HashMap[Node, Int]

var isCheckingPorts: Boolean

var isClockGatingUpdates: Boolean

var isClockGatingUpdatesInline: Boolean

var isCompiling: Boolean

var isDebug: Boolean

var isEmittingComponents: Boolean

var isFolding: Boolean

var isGenHarness: Boolean

var isInlineMem: Boolean

final def isInstanceOf[T0]: Boolean

var isIoDebug: Boolean

var isPruning: Boolean

var isReportDims: Boolean

def isSubclassOfModule(x: Class[_]): Boolean

var isTesting: Boolean

var isVCD: Boolean

val keywords: HashSet[String]

val muxes: ArrayBuffer[Node]

final def ne(arg0: AnyRef): Boolean

val nodes: ArrayBuffer[Node]

final def notify(): Unit

final def notifyAll(): Unit

def pop(): Unit

var printArgs: ArrayBuffer[Node]

var printFormat: String

var printStackStruct: ArrayBuffer[(Int, Module)]

val printfs: ArrayBuffer[Printf]

val procs: ArrayBuffer[proc]

val randInitIOs: ArrayBuffer[Node]

val resetList: ArrayBuffer[Node]

var saveComponentTrace: Boolean

var saveConnectionWarnings: Boolean

var saveWidthWarnings: Boolean

var scanArgs: ArrayBuffer[Node]

var scanFormat: String

var searchAndMap: Boolean

def setAsTopComponent(mod: Module): Unit

var sortedComps: ArrayBuffer[Module]

def splitArg(s: String): List[String]

var stackIndent: Int

final def synchronized[T0](arg0: ⇒ T0): T0

var targetDir: String

var tester: Tester[Module]

def toString(): String

var topComponent: Module

var trigger: Boolean

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit