object
chiselMain
Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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def
apply[T <: Module](args: Array[String], gen: () ⇒ T, scanner: (T) ⇒ TestIO = null, printer: (T) ⇒ TestIO = null, ftester: (T) ⇒ Tester[T] = null): T
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final
def
asInstanceOf[T0]: T0
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def
clone(): AnyRef
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
finalize(): Unit
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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final
def
isInstanceOf[T0]: Boolean
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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def
readArgs(args: Array[String]): Unit
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def
run[T <: Module](args: Array[String], gen: () ⇒ T): T
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
Inherited from AnyRef
Inherited from Any
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter. That execution tree is simplified by aggregating all calls which are not constructors of a Module instance into the parent which is. The simplified tree (encoded through _Module.children_) forms the basis of the generated verilog. Each node in the simplified execution tree is a _Module_ instance from which a verilog module is textually derived. As an optimization, _Backend_ classes output modules which are textually equivalent only once and update a _Module_ instance's _moduleName_ accordingly.