!=

Bits SInt

##

Bits Data Node

%

Bits SInt UInt

&

Bits

&&

Bool

*

Bits Clock SInt UInt

+

Bits Bundle SInt UInt

+=

Bundle

-

Bits SInt UInt

-=

Bundle

/

Bits Clock SInt UInt

::

Mux

:=

Bits Bool Bundle Data SInt UInt Vec

<

SInt UInt

<<

SInt UInt

<=

SInt UInt

<>

Bits Bundle Module Node Vec

===

Bits Data SInt UInt

>

SInt UInt

>=

SInt UInt

>>

SInt UInt

?

SInt UInt

^

Bits

^^

Bundle Node Vec

|

Bits

||

Bool