Instance Constructors
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new
FPGABackend()
Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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final
def
asInstanceOf[T0]: T0
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def
asValidName(name: String): String
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def
assignClockAndResetToModules: Unit
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def
checkPorts(topC: Module): Unit
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def
clone(): AnyRef
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def
collectNodesIntoComp(dfsStack: Stack[Node]): Unit
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val
compIndices: HashMap[String, Int]
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def
compile(c: Module, flags: String): Unit
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def
connectResets: Unit
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def
createClkDomain(root: Node, walked: ArrayBuffer[Node]): Unit
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def
createOutputFile(name: String): FileWriter
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def
depthString(depth: Int): String
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def
doCompile(top: Module, out: FileWriter, depth: Int): Unit
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def
elaborate(c: Module): Unit
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def
emitChildren(top: Module, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit
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def
emitDec(node: Node): String
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def
emitDecBase(node: Node): String
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def
emitDecs(c: Module): StringBuilder
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def
emitDef(node: Node): String
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def
emitDef(c: Module): String
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def
emitDefs(c: Module): StringBuilder
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def
emitModuleText(c: Module): String
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def
emitPortDef(m: MemAccess, idx: Int): String
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def
emitRef(node: Node): String
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def
emitRef(c: Module): String
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def
emitReg(node: Node): String
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def
emitRegs(c: Module): StringBuilder
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def
emitSigned(n: Node): String
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def
emitTmp(node: Node): String
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def
emitWidth(node: Node): String
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def
ensureDir(dir: String): String
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
extractClassName(comp: Module): String
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def
finalize(): Unit
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def
flushModules(out: FileWriter, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit
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val
flushedTexts: HashSet[String]
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def
fullyQualifiedName(m: Node): String
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def
gatherChildren(root: Module): ArrayBuffer[Module]
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def
gatherClocksAndResets: Unit
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def
genHarness(c: Module, name: String): Unit
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def
genIndent(x: Int): String
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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def
initializeDFS: Stack[Node]
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final
def
isInstanceOf[T0]: Boolean
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def
isMultiWrite(m: Mem[_]): Boolean
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val
keywords: HashSet[String]
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def
levelChildren(root: Module): Unit
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val
memConfs: HashMap[String, String]
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def
nameAll(root: Module): Unit
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def
nameChildren(root: Module): Unit
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def
nameRsts: Unit
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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def
printStack: Unit
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def
pruneNodes: Unit
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def
pruneUnconnectedIOs(m: Module): Unit
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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def
transform(c: Module, transforms: ArrayBuffer[(Module) ⇒ Unit]): Unit
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val
transforms: ArrayBuffer[(Module) ⇒ Unit]
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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def
writeMap(m: Mem[_], exclude: Int = 1): Seq[String]
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def
writen(m: MemWrite): Int
Inherited from AnyRef
Inherited from Any