CounterVBackend

Instance Constructors

new CounterVBackend()

Value Members

final def !=(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def !=(arg0: Any): Boolean

Definition Classes
Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def ==(arg0: Any): Boolean

Definition Classes
Any
def addPin(m: Module, pin: Data, name: String): Unit

Definition Classes
CounterBackend
def addReg(m: Module, outType: Bits, name: String = "", updates: Map[Bool, Node] = Map()): Unit

Definition Classes
CounterBackend
val analyses: ArrayBuffer[(Module) ⇒ Unit]

Definition Classes
Backend
final def asInstanceOf[T0]: T0

Definition Classes
Any
def asValidName(name: String): String

Definition Classes
Backend
def assignClockAndResetToModules: Unit

Definition Classes
Backend
def backannotationAnalyses: Unit

Definition Classes
Backend
def backannotationTransforms: Unit

Definition Classes
CounterBackend → Backend
def checkPorts(topC: Module): Unit

Definition Classes
Backend
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

Definition Classes
Backend
val compIndices: HashMap[String, Int]

Definition Classes
VerilogBackend
def compile(c: Module, flags: String): Unit

Definition Classes
VerilogBackend → Backend
def connectConsumers(input: Node, via: Node): Unit

Definition Classes
CounterBackend
def connectDaisyPins(c: Module): Unit

Definition Classes
CounterBackend
def connectResets: Unit

Definition Classes
Backend
val counterCopy: HashMap[Module, Bool]

Definition Classes
CounterBackend
var counterIdx: Int

Definition Classes
CounterBackend
val counterRead: HashMap[Module, Bool]

Definition Classes
CounterBackend
def createOutputFile(name: String): FileWriter

Definition Classes
FileSystemUtilities
val daisyCtrls: HashMap[Module, Bits]

Definition Classes
CounterBackend
val daisyIns: HashMap[Module, UInt]

Definition Classes
CounterBackend
val daisyOuts: HashMap[Module, DecoupledIO[UInt]]

Definition Classes
CounterBackend
def decoupleTarget(c: Module): Unit

Definition Classes
CounterBackend
val decoupledPins: HashMap[Node, Bits]

Definition Classes
CounterBackend
def depthString(depth: Int): String

Definition Classes
Backend
def doCompile(top: Module, out: FileWriter, depth: Int): Unit

Definition Classes
VerilogBackend
def elaborate(c: Module): Unit

Definition Classes
VerilogBackend → Backend
def emitAssert(a: Assert): String

Definition Classes
VerilogBackend
def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

Definition Classes
VerilogBackend
def emitCounterIdx: Int

Definition Classes
CounterBackend
def emitDec(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitDecBase(node: Node, wire: String = "wire"): String

Definition Classes
VerilogBackend
def emitDecReg(node: Node): String

Definition Classes
VerilogBackend
def emitDecs(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitDef(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitDef(c: Module): String

Definition Classes
VerilogBackend
def emitDefs(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitInit(node: Node): String

Definition Classes
VerilogBackend
def emitInits(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitModuleText(c: Module): String

Definition Classes
VerilogBackend
def emitPortDef(m: MemAccess, idx: Int): String

Definition Classes
VerilogBackend
def emitPrintf(p: Printf): String

Definition Classes
VerilogBackend
def emitRef(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitRef(c: Module): String

Definition Classes
Backend
def emitReg(node: Node): String

Definition Classes
VerilogBackend
def emitRegs(c: Module): StringBuilder

Definition Classes
VerilogBackend
def emitTmp(node: Node): String

Definition Classes
VerilogBackend → Backend
def emitWidth(node: Node): String

Definition Classes
VerilogBackend
def ensureDir(dir: String): String

Ensures a directory *dir* exists on the filesystem.
Ensures a directory *dir* exists on the filesystem.

Definition Classes
FileSystemUtilities
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

Definition Classes
Backend
def extractClassName(comp: Module): String

Definition Classes
Backend
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
val firedPins: HashMap[Module, Bool]

Definition Classes
CounterBackend
def flushModules(out: FileWriter, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

Definition Classes
VerilogBackend
val flushedTexts: HashSet[String]

Definition Classes
VerilogBackend
def fullyQualifiedName(m: Node): String

Definition Classes
Backend
def gatherChildren(root: Module): ArrayBuffer[Module]

Definition Classes
Backend
def gatherClocksAndResets: Unit

Definition Classes
Backend
def genHarness(c: Module, name: String): Unit

Definition Classes
VerilogBackend
def genIndent(x: Int): String

Attributes
protected
Definition Classes
Backend
def generateCounters(c: Module): Unit

Definition Classes
CounterBackend
def generateDaisyChains(c: Module): Unit

Definition Classes
CounterBackend
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getPseudoPath(c: Module, delim: String = "/"): String

Definition Classes
Backend
def getSignalPathName(n: Node, delim: String = "/", isRealName: Boolean = false): String

Definition Classes
Backend
def harnessAPIs(mainClk: Clock, clocks: LinkedHashSet[Clock], resets: ArrayBuffer[Bool], wires: ArrayBuffer[Node], mems: ArrayBuffer[Mem[_]], scanNodes: Array[Bits], printNodes: Array[Bits]): String

Definition Classes
VerilogBackend
def harnessMap(mainClk: Clock, resets: ArrayBuffer[Bool], scanNodes: Array[Bits], printNodes: Array[Bits]): String

* Test bench for replay **
* Test bench for replay **

Definition Classes
VerilogBackend
def hashCode(): Int

Definition Classes
AnyRef → Any
def initBackannotation: Unit

Definition Classes
Backend
def initializeDFS: Stack[Node]

Definition Classes
Backend
def isBitsIo(node: Node, dir: IODirection): Boolean

Nodes which are created outside the execution trace from the toplevel component constructor (i.
Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.
This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).
We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.
Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

Definition Classes
Backend
def isEmittingComponents: Boolean

Definition Classes
VerilogBackend → Backend
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
val keywords: HashSet[String]

Definition Classes
VerilogBackend → Backend
def levelChildren(root: Module): Unit

Definition Classes
Backend
val memConfs: HashMap[String, String]

Definition Classes
VerilogBackend
def nameAll(root: Module): Unit

Definition Classes
Backend
def nameChildren(root: Module): Unit

Definition Classes
Backend
def nameRsts: Unit

Definition Classes
Backend
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val needsLowering: Set[String]

Definition Classes
VerilogBackend → Backend
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val preElaborateTransforms: ArrayBuffer[(Module) ⇒ Unit]

Definition Classes
Backend
def printStack: Unit

Prints the call stack of Component as seen by the push/pop runtime.
Prints the call stack of Component as seen by the push/pop runtime.

Attributes
protected
Definition Classes
Backend
def pruneNodes: Unit

Definition Classes
Backend
def pruneUnconnectedIOs(m: Module): Unit

Definition Classes
Backend
def setPseudoNames(c: Module): Unit

Definition Classes
Backend
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
val transforms: ArrayBuffer[(Module) ⇒ Unit]

Definition Classes
Backend
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def wirePin(pin: Data, input: Node): Unit

Definition Classes
CounterBackend
def writeOutGraph(c: Module): Unit

Definition Classes
Backend

class CounterVBackend extends VerilogBackend with CounterBackend

Instance Constructors

new CounterVBackend()

Value Members

final def !=(arg0: AnyRef): Boolean

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: AnyRef): Boolean

final def ==(arg0: Any): Boolean

def addPin(m: Module, pin: Data, name: String): Unit

def addReg(m: Module, outType: Bits, name: String = "", updates: Map[Bool, Node] = Map()): Unit

val analyses: ArrayBuffer[(Module) ⇒ Unit]

final def asInstanceOf[T0]: T0

def asValidName(name: String): String

def assignClockAndResetToModules: Unit

def backannotationAnalyses: Unit

def backannotationTransforms: Unit

def checkPorts(topC: Module): Unit

def clone(): AnyRef

def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

val compIndices: HashMap[String, Int]

def compile(c: Module, flags: String): Unit

def connectConsumers(input: Node, via: Node): Unit

def connectDaisyPins(c: Module): Unit

def connectResets: Unit

val counterCopy: HashMap[Module, Bool]

var counterIdx: Int

val counterRead: HashMap[Module, Bool]

def createOutputFile(name: String): FileWriter

val daisyCtrls: HashMap[Module, Bits]

val daisyIns: HashMap[Module, UInt]

val daisyOuts: HashMap[Module, DecoupledIO[UInt]]

def decoupleTarget(c: Module): Unit

val decoupledPins: HashMap[Node, Bits]

def depthString(depth: Int): String

def doCompile(top: Module, out: FileWriter, depth: Int): Unit

def elaborate(c: Module): Unit

def emitAssert(a: Assert): String

def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

def emitCounterIdx: Int

def emitDec(node: Node): String

def emitDecBase(node: Node, wire: String = "wire"): String

def emitDecReg(node: Node): String

def emitDecs(c: Module): StringBuilder

def emitDef(node: Node): String

def emitDef(c: Module): String

def emitDefs(c: Module): StringBuilder

def emitInit(node: Node): String

def emitInits(c: Module): StringBuilder

def emitModuleText(c: Module): String

def emitPortDef(m: MemAccess, idx: Int): String

def emitPrintf(p: Printf): String

def emitRef(node: Node): String

def emitRef(c: Module): String

def emitReg(node: Node): String

def emitRegs(c: Module): StringBuilder

def emitTmp(node: Node): String

def emitWidth(node: Node): String

def ensureDir(dir: String): String

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

def extractClassName(comp: Module): String

def finalize(): Unit

val firedPins: HashMap[Module, Bool]

def flushModules(out: FileWriter, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

val flushedTexts: HashSet[String]

def fullyQualifiedName(m: Node): String

def gatherChildren(root: Module): ArrayBuffer[Module]

def gatherClocksAndResets: Unit

def genHarness(c: Module, name: String): Unit

def genIndent(x: Int): String

def generateCounters(c: Module): Unit

def generateDaisyChains(c: Module): Unit

final def getClass(): Class[_]

def getPseudoPath(c: Module, delim: String = "/"): String

def getSignalPathName(n: Node, delim: String = "/", isRealName: Boolean = false): String

def harnessAPIs(mainClk: Clock, clocks: LinkedHashSet[Clock], resets: ArrayBuffer[Bool], wires: ArrayBuffer[Node], mems: ArrayBuffer[Mem[_]], scanNodes: Array[Bits], printNodes: Array[Bits]): String

def harnessMap(mainClk: Clock, resets: ArrayBuffer[Bool], scanNodes: Array[Bits], printNodes: Array[Bits]): String