Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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val
CC: String
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val
CCFLAGS: String
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val
CPPFLAGS: String
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val
CXX: String
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val
CXXFLAGS: String
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val
LDFLAGS: String
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var
allocateOnlyNeededShadowRegisters: Boolean
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def
appendString(s1: Option[String], s2: Option[String]): String
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def
apply[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T], wrapped: Boolean): T
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def
apply[T <: Module](args: Array[String], gen: () ⇒ T, wrapped: Boolean): T
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final
def
asInstanceOf[T0]: T0
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def
bfs(visit: (Node) ⇒ Unit): Unit
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val
blackboxes: ArrayBuffer[BlackBox]
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def
cc(dir: String, name: String, flags: String = "", isCC: Boolean = false): Unit
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var
chiselConfigClassName: Option[String]
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var
chiselConfigDump: Boolean
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var
chiselConfigMode: Option[String]
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val
chiselENV: String
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val
chiselOneHotBitMap: HashMap[(Bits, Int), Bool]
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val
chiselOneHotMap: HashMap[(UInt, Int), UInt]
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var
chiselProjectName: Option[String]
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val
clocks: ArrayBuffer[Clock]
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def
clone(): AnyRef
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val
compStack: Stack[Module]
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var
compileInitializationUnoptimized: Boolean
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val
components: ArrayBuffer[Module]
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def
copyToTarget(filename: String): Unit
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def
createOutputFile(name: String): FileWriter
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def
dfs(visit: (Node) ⇒ Unit): Unit
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var
dontFindCombLoop: Boolean
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var
dumpTestInput: Boolean
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def
elapsedTime: Long
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var
emitTempNodes: Boolean
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def
ensureDir(dir: String): String
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
finalize(): Unit
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def
getArg(s: String, i: Int): String
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final
def
getClass(): Class[_]
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var
getLineNumbers: Boolean
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def
getNodeId: Int
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def
hashCode(): Int
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def
idfs(visit: (Node) ⇒ Unit): Unit
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val
implicitClock: Clock
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val
implicitReset: Bool
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var
includeArgs: List[String]
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def
initChisel(args: Array[String]): Unit
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var
isAssert: Boolean
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var
isAssertWarn: Boolean
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var
isCSE: Boolean
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var
isCheckingPorts: Boolean
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def
isCommandAvailable(cmd: String): Boolean
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var
isCompiling: Boolean
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var
isDebug: Boolean
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var
isDebugMem: Boolean
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var
isGenHarness: Boolean
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var
isInGetWidth: Boolean
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var
isInlineMem: Boolean
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final
def
isInstanceOf[T0]: Boolean
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var
isIoDebug: Boolean
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var
isReportDims: Boolean
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var
isSupportW0W: Boolean
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var
isTesting: Boolean
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var
isVCD: Boolean
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var
isVCDMem: Boolean
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var
isVCDinline: Boolean
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lazy val
isVCSAvailable: Boolean
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var
lineLimitFunctions: Int
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def
link(dir: String, target: String, objects: Seq[String], isCC: Boolean = false, isLib: Boolean = false): Unit
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var
minimumCompatibility: Version
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var
minimumLinesPerFile: Int
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var
modAdded: Boolean
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var
modStackPushed: Boolean
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var
moduleNamePrefix: String
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final
def
ne(arg0: AnyRef): Boolean
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var
nodeId: Int
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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val
orderedNodes: ArrayBuffer[Node]
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val
parStack: Stack[Parameters]
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var
parallelMakeJobs: Int
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var
partitionIslands: Boolean
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val
printStackStruct: ArrayBuffer[(Int, Module)]
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def
run(cmd: String): Boolean
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var
saveComponentTrace: Boolean
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var
saveConnectionWarnings: Boolean
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def
setTopComponent(mod: Module): Unit
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var
shadowRegisterInObject: Boolean
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val
signalMap: LinkedHashMap[Node, Int]
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val
sortedComps: ArrayBuffer[Module]
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var
stackIndent: Int
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var
startTime: Long
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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var
targetDir: String
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var
testCommand: Option[String]
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var
testerSeed: Long
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def
toString(): String
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var
topComponent: Option[Module]
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var
useSimpleQueue: Boolean
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var
wError: Boolean
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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def
wantLineNumbers: Boolean
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var
warnInputs: Boolean
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var
warnOutputs: Boolean
Inherited from AnyRef
Inherited from Any