class
VerilogBackend extends Backend
Instance Constructors
-
new
VerilogBackend()
Value Members
-
final
def
!=(arg0: AnyRef): Boolean
-
final
def
!=(arg0: Any): Boolean
-
final
def
##(): Int
-
final
def
==(arg0: AnyRef): Boolean
-
final
def
==(arg0: Any): Boolean
-
val
CC: String
-
val
CCFLAGS: String
-
val
CPPFLAGS: String
-
val
CXX: String
-
val
CXXFLAGS: String
-
val
LDFLAGS: String
-
def
W0Wtransform(): Unit
-
def
addBindings: Unit
-
def
addClocksAndResets: Unit
-
def
addDefaultResets: Unit
-
val
analyses: ArrayBuffer[(Module) ⇒ Unit]
-
final
def
asInstanceOf[T0]: T0
-
def
asValidName(name: String): String
-
def
assignClockAndResetToModules: Unit
-
def
cc(dir: String, name: String, flags: String = "", isCC: Boolean = false): Unit
-
def
checkModuleResolution: Unit
-
def
checkPorts: Unit
-
val
chiselENV: String
-
def
clone(): AnyRef
-
def
collectNodesIntoComp(mod: Module): Unit
-
val
compIndices: HashMap[String, Int]
-
def
compile(c: Module, flags: Option[String]): Unit
-
def
computeMemPorts(mod: Module): Unit
-
def
connectResets: Unit
-
def
convertMaskedWrites(mod: Module): Unit
-
def
copyToTarget(filename: String): Unit
-
def
createOutputFile(name: String): FileWriter
-
def
delimitUncommentedPortDecls(portDecls: ArrayBuffer[StringBuilder]): Unit
-
def
doCompile(top: Module, out: FileWriter, depth: Int): Unit
-
def
elaborate(c: Module): Unit
-
def
emitAssert(a: Assert): String
-
def
emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit
-
def
emitDec(node: Node): String
-
def
emitDecBase(node: Node, wire: String = "wire"): String
-
def
emitDecReg(node: Node): String
-
def
emitDecs(c: Module): StringBuilder
-
def
emitDef(node: Node): String
-
def
emitDef(c: Module): StringBuilder
-
def
emitDefs(c: Module): StringBuilder
-
def
emitInit(node: Node): String
-
def
emitInits(c: Module): StringBuilder
-
def
emitModuleText(c: Module): StringBuilder
-
def
emitPortDef(m: MemAccess, idx: Int): String
-
def
emitPrintf(p: Printf): String
-
def
emitRef(node: Node): String
-
def
emitRef(c: Module): String
-
def
emitReg(node: Node): String
-
def
emitRegs(c: Module): StringBuilder
-
def
emitTmp(node: Node): String
-
def
emitWidth(node: Node): String
-
val
emittedModules: HashSet[String]
-
def
ensureDir(dir: String): String
-
final
def
eq(arg0: AnyRef): Boolean
-
def
equals(arg0: Any): Boolean
-
def
execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit
-
def
extractClassName(comp: Module): String
-
def
finalize(): Unit
-
def
findCombLoop: Unit
-
def
findConsumers(mod: Module): Unit
-
def
findGraphDims: (Int, Int, Int)
-
def
flattenAll: Unit
-
def
flushModules(defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], level: Int): Unit
-
def
forceMatchingWidths: Unit
-
def
fullyQualifiedName(m: Node): String
-
def
gatherClocksAndResets: Unit
-
def
genHarness(c: Module, name: String): Unit
-
def
genIndent(x: Int): String
-
final
def
getClass(): Class[_]
-
def
hashCode(): Int
-
def
inferAll(mod: Module): Int
-
def
isBitsIo(node: Node, dir: IODirection): Boolean
-
def
isEmittingComponents: Boolean
-
def
isInObject(n: Node): Boolean
-
final
def
isInstanceOf[T0]: Boolean
-
val
keywords: Set[String]
-
def
link(dir: String, target: String, objects: Seq[String], isCC: Boolean = false, isLib: Boolean = false): Unit
-
def
lowerNodes(mod: Module): Unit
-
def
markComponents: Unit
-
val
memConfs: HashMap[String, String]
-
def
nameAll(): Unit
-
def
nameBindings: Unit
-
def
nameRsts: Unit
-
val
nameSpace: HashSet[String]
-
final
def
ne(arg0: AnyRef): Boolean
-
val
needsLowering: Set[String]
-
final
def
notify(): Unit
-
final
def
notifyAll(): Unit
-
def
printStack: Unit
-
def
pruneUnconnectedIOs: Unit
-
def
removeTypeNodes(mod: Module): Int
-
def
renameNodes(nodes: Seq[Node], sep: String = "_"): Unit
-
def
run(cmd: String): Boolean
-
def
sortComponents: Unit
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
-
def
synthesizeable(node: Node): Boolean
-
def
toString(): String
-
-
val
transforms: ArrayBuffer[(Module) ⇒ Unit]
-
def
verifyAllMuxes: Unit
-
def
verifyComponents: Unit
-
final
def
wait(): Unit
-
final
def
wait(arg0: Long, arg1: Int): Unit
-
final
def
wait(arg0: Long): Unit
Inherited from AnyRef
Inherited from Any