verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
- HashMap of source lines (and associated nodes) requiring Wire() wrapping.
Connect io with matching names for two modules
Connect io with matching names for two modules
Add a clock to the module
Add a default reset to the module
Add a default reset to the module
Add a submodule to this module
Add a submodule to this module
Add a submodule to this module
Add a submodule to this module
Add a pin with a name to the module
the pin connected to the reset signal or creates a new one if no such pin exists
Add an assertion in the code generated by a backend.
Add an assertion in the code generated by a backend.
A breadth first search of the graph of nodes
A breadth first search of the graph of nodes
Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes
the implied clock for this module
Insures a backend does not remove a signal because it is unreachable from the outputs.
Insures a backend does not remove a signal because it is unreachable from the outputs.
A depth first search of the graph of nodes
A depth first search of the graph of nodes
A method to trace the graph of nodes backwards looking at inputs
A method to trace the graph of nodes backwards looking at inputs
Node to find bindings for
nodes which have node m binded as their input
this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid
this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid
Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes
The separator to use for the path name
the absolute path to a component instance from toplevel
the absolute path to a component instance from toplevel
the I/O for this module
the I/O for this module
Name of the module this component generates (defaults to class name).
Name of the module this component generates (defaults to class name).
Name of the instance.
Name of the instance.
named is used to indicate that name was set explicitly and should not be overriden
named is used to indicate that name was set explicitly and should not be overriden
Adds a printf to the module called each clock cycle
Adds a printf to the module called each clock cycle
A c style sting to print out eg) %d, %x
Nodes whos data values should be printed
iterate over recorded events, checking constraints on ports referenced, etc.
iterate over recorded events, checking constraints on ports referenced, etc. use poke and expect to record
the implied reset for this module
Set the declaration name of the module to be string 'n'
Set the declaration name of the module to be string 'n'
Set the name of this module to the string 'n'
Set the name of this module to the string 'n'
my.io.node.setName("MY_IO_NODE")
Ends the test reporting success.
Ends the test reporting success.
Does not fire when in reset (defined as the encapsulating Module's reset). If your definition of reset is not the encapsulating Module's reset, you will need to gate this externally.
Get the I/O names and connections
Get the I/O names and connections
Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated
an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time
independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created