verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
- HashMap of source lines (and associated nodes) requiring Wire() wrapping.
Connect io with matching names for two modules
Connect io with matching names for two modules
Add a clock to the module
Add a default reset to the module
Add a default reset to the module
Add a submodule to this module
Add a submodule to this module
Add a submodule to this module
Add a submodule to this module
Add a pin with a name to the module
the pin connected to the reset signal or creates a new one if no such pin exists
Add an assertion in the code generated by a backend.
Add an assertion in the code generated by a backend.
A breadth first search of the graph of nodes
A breadth first search of the graph of nodes
the implied clock for this module
Insures a backend does not remove a signal because it is unreachable from the outputs.
Insures a backend does not remove a signal because it is unreachable from the outputs.
A depth first search of the graph of nodes
A depth first search of the graph of nodes
A method to trace the graph of nodes backwards looking at inputs
A method to trace the graph of nodes backwards looking at inputs
Node to find bindings for
nodes which have node m binded as their input
The separator to use for the path name
the absolute path to a component instance from toplevel
the absolute path to a component instance from toplevel
the I/O for this module
the I/O for this module
Name of the module this component generates (defaults to class name).
Name of the module this component generates (defaults to class name).
Name of the instance.
Name of the instance.
named is used to indicate that name was set explicitly and should not be overriden
named is used to indicate that name was set explicitly and should not be overriden
Adds a printf to the module called each clock cycle
Adds a printf to the module called each clock cycle
A c style sting to print out eg) %d, %x
Nodes whos data values should be printed
the implied reset for this module
Set the declaration name of the module to be string 'n'
Set the declaration name of the module to be string 'n'
Set the name of this module to the string 'n'
Set the name of this module to the string 'n'
my.io.node.setName("MY_IO_NODE")
Ends the test reporting success.
Ends the test reporting success.
Does not fire when in reset (defined as the encapsulating Module's reset). If your definition of reset is not the encapsulating Module's reset, you will need to gate this externally.
Get the I/O names and connections
Get the I/O names and connections
Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes