OrderedDecoupledHWIOTester

abstract val device_under_test: Module

final def !=(arg0: AnyRef): Boolean

final def !=(arg0: Any): Boolean

final def ##(): Int

def <>(src: Module): Unit

Connect io with matching names for two modules

final def ==(arg0: AnyRef): Boolean

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): iodef.type

var _clock: Option[Clock]

def addClock(clock: Clock): Unit

Add a clock to the module

def addDefaultReset: Unit

Add a default reset to the module

def addModule[T <: Module](c: ⇒ T)(implicit p: Parameters = params): T

Add a submodule to this module

def addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T

Add a submodule to this module

def addNode[T <: Node](node: T): T

def addPin[T <: Data](pin: T, name: String = ""): T

Add a pin with a name to the module

def addResetPin(r: Bool): Bool

def apply(name: String): Data

final def asInstanceOf[T0]: T0

def assert(cond: Bool, message: String = ""): Unit

Add an assertion in the code generated by a backend.

def bfs(visit: (Node) ⇒ Unit): Unit

A breadth first search of the graph of nodes

def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, BigInt)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes

val children: ArrayBuffer[Module]

def clock: Clock

def clone(): AnyRef

val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]

def debug(data: Aggregate): Unit

def debug(x: Node): Unit

Insures a backend does not remove a signal because it is unreachable from the outputs.

val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]

def dfs(visit: (Node) ⇒ Unit): Unit

A depth first search of the graph of nodes

var enable_all_debug: Boolean

var enable_printf_debug: Boolean

var enable_scala_debug: Boolean

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def error(message: String = ""): Unit

def finalize(): Unit

def findBinding(m: Node): Option[Binding]

A method to trace the graph of nodes backwards looking at inputs

def finish(): Unit

this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

final def getClass(): Class[_]

def getCommonValidParentPort(expects: Seq[(Data, BigInt)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes

def getPathName(separator: String = "_"): String

def getPathName: String

val hashCode: Int

def inputEvent(pokes: (Data, BigInt)*): Unit

val input_event_list: ArrayBuffer[Seq[(Data, BigInt)]]

def int(x: Bits): BigInt

val io: Bundle { ... /* 4 definitions in type refinement */ }

the I/O for this module

var io_info: IOAccessor

final def isInstanceOf[T0]: Boolean

def logPrintfDebug(fmt: String, args: Bits*): Unit

def logScalaDebug(msg: ⇒ String): Unit

var moduleName: String

Name of the module this component generates (defaults to class name).

var name: String

Name of the instance.

var named: Boolean

named is used to indicate that name was set explicitly and should not be overriden

final def ne(arg0: AnyRef): Boolean

def nextIndex: Int

final def notify(): Unit

final def notifyAll(): Unit

def outputEvent(expects: (Data, BigInt)*): Unit

val output_event_list: ArrayBuffer[Seq[(Data, BigInt)]]

lazy val params: Parameters

var parent: Module

def popCount(n: Long): Int

val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]

val port_to_valid: HashMap[Data, ValidIO[Data]]

def printf(message: String, args: Node*): Unit

Adds a printf to the module called each clock cycle

def processInputEvents(): Unit

iterate over recorded events, checking constraints on ports referenced, etc.

def processOutputEvents(): Unit

def reset: Bool

val rnd: Random

val setDone: Bool

val setError: Bool

def setModuleName(n: String): Unit

Set the declaration name of the module to be string 'n'

def setName(n: String): Unit

Set the name of this module to the string 'n'

def stop(): Unit

Ends the test reporting success.

def stripComponent(s: String): String

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def wires: Array[(String, Bits)]

Get the I/O names and connections