Hardware module that is used to sequence n producers into 1 consumer.
Base class for built-in Chisel types Bits and SInt.
Defines a collection of datum of different types into a single coherent whole.
*Data* is part of the *Node* Composite Pattern class hierarchy.
Stores the actual value of a scala literal as a string.
*Node* defines the root class of the class hierarchy for a [Composite Pattern](http://en.
Hardware module that is used to sequence n producers into 1 consumer.
This Singleton implements a log4j compatible interface.
Adds a ready-valid handshaking protocol to any interface.
linear feedback shift register
*seqRead* means that if a port tries to read the same address that another port is writing to in the same cycle, the read data is random garbage (from a LFSR, which returns "1" on its first invocation).
Builds a Mux tree out of the input signal vector using a one hot encoded select signal.
Does the inverse of UIntToOH.
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter.
Returns the number of bits set (i.
Returns the bit position of the trailing 1 in the input vector with the assumption that multiple bits of the input bit vector can be set
Returns a bit vector in which only the least-significant 1 bit in the input vector, if any, is set.
Builds a Mux tree under the assumption that multiple select signals can be enabled.
Generic hardware queue.
Litte/big bit endian convertion: reverse the order of the bits in a UInt.
Returns the n-cycle delayed version of the input signal.
Returns the one hot encoding of the input UInt.
Adds a valid protocol to any interface.
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter.