Class

chiseltest.experimental

AsyncResetReg

Related Doc: package experimental

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class AsyncResetReg extends ExtModule

This is a black box example that only works with treadle as it does not define the necessary verilog for verilator/VCS

Should be API compatible with rocket-chip's AsyncResetReg

Linear Supertypes
ExtModule, BaseBlackBox, BaseModule, HasId, InstanceId, AnyRef, Any
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Inherited
  1. AsyncResetReg
  2. ExtModule
  3. BaseBlackBox
  4. BaseModule
  5. HasId
  6. InstanceId
  7. AnyRef
  8. Any
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Visibility
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Instance Constructors

  1. new AsyncResetReg(resetValue: Int = 0)

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    resetValue

    reset value for this 1 bit register

Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  4. def IO[T <: Data](iodef: T): T

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    Attributes
    protected
    Definition Classes
    BaseModule

  5. def _bindIoInPlace(iodef: Data): Unit

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    Attributes
    protected
    Definition Classes
    BaseModule

  6. var _closed: Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule

  7. def _compatAutoWrapPorts(): Unit

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    Definition Classes
    BaseModule

  8. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any

  9. def circuitName: String

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    Attributes
    protected
    Definition Classes
    HasId

  10. val clk: Clock

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  11. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  12. val d: UInt

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  13. def desiredName: String

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    Definition Classes
    BaseModule

  14. val en: Bool

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  15. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  16. def equals(that: Any): Boolean

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    Definition Classes
    HasId → AnyRef → Any

  17. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  18. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any

  19. def getIds: Seq[HasId]

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    Attributes
    protected
    Definition Classes
    BaseModule

  20. def getModulePorts: Seq[Data]

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    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule

  21. def hashCode(): Int

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    Definition Classes
    HasId → AnyRef → Any

  22. def instanceName: String

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    Definition Classes
    BaseModule → HasId → InstanceId

  23. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any

  24. final lazy val name: String

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    Definition Classes
    BaseModule

  25. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

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    Attributes
    protected
    Definition Classes
    BaseModule

  26. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  27. final def notify(): Unit

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    Definition Classes
    AnyRef

  28. final def notifyAll(): Unit

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    Definition Classes
    AnyRef

  29. val params: Map[String, Param]

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    Definition Classes
    ExtModule

  30. def parentModName: String

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    Definition Classes
    HasId → InstanceId

  31. def parentPathName: String

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    Definition Classes
    HasId → InstanceId

  32. def pathName: String

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    Definition Classes
    HasId → InstanceId

  33. def portsContains(elem: Data): Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule

  34. def portsSize: Int

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    Attributes
    protected
    Definition Classes
    BaseModule

  35. val q: UInt

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  36. val rst: Bool

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  37. def suggestName(name: ⇒ String): AsyncResetReg.this.type

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    Definition Classes
    HasId

  38. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef

  39. final def toAbsoluteTarget: IsModule

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    Definition Classes
    BaseModule → InstanceId

  40. final def toNamed: ModuleName

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    Definition Classes
    BaseModule → InstanceId

  41. def toString(): String

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    Definition Classes
    AnyRef → Any

  42. final def toTarget: ModuleTarget

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    Definition Classes
    BaseModule → InstanceId

  43. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  44. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  45. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from ExtModule

Inherited from BaseBlackBox

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

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