VerilatorExecutive

Value Members

1. final def !=(arg0: Any): Boolean

   

   Definition Classes

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2. final def ##(): Int

   

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3. final def ==(arg0: Any): Boolean

   

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4. final def asInstanceOf[T0]: T0

   

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5. def clone(): AnyRef

   

   Attributes

   protected[java.lang]

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   Annotations

   @throws( ... )

6. def combinationalPathsToData(dut: BaseModule, paths: Seq[CombinationalPath], dataNames: Map[Data, String], componentToName: (ReferenceTarget) ⇒ String): Map[Data, Set[Data]]

   

   This creates some kind of map of combinational paths between inputs and outputs.

   This creates some kind of map of combinational paths between inputs and outputs.

   dut

   use this to figure out which paths involve top level iO

   paths

   combinational paths found by firrtl pass CheckCombLoops

   dataNames

   a map between a port's Data and it's string name

   componentToName

   used to map ReferenceTargets found in paths into correct local string form

   Definition Classes

   BackendExecutive

7. def componentToName(component: ReferenceTarget): String

   

   Verilator wants to have module name prefix except for default reset and clock

   Verilator wants to have module name prefix except for default reset and clock

   component

   signal name to be mapped into backend string form

8. final def eq(arg0: AnyRef): Boolean

   

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9. def equals(arg0: Any): Boolean

   

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10. def finalize(): Unit

    

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    protected[java.lang]

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    @throws( classOf[java.lang.Throwable] )

11. final def getClass(): Class[_]

    

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12. def getDataNames(name: String, data: Data): Seq[(Data, String)]

    

    Returns a Seq of (data reference, fully qualified element names) for the input.

    Returns a Seq of (data reference, fully qualified element names) for the input. name is the name of data

    Definition Classes

    BackendExecutive

13. def getTopModule(circuit: Circuit): BaseModule

    

    Definition Classes

    BackendExecutive

14. def hashCode(): Int

    

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15. final def isInstanceOf[T0]: Boolean

    

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16. final def ne(arg0: AnyRef): Boolean

    

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17. final def notify(): Unit

    

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18. final def notifyAll(): Unit

    

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19. def start[T <: MultiIOModule](dutGen: () ⇒ T, annotationSeq: AnnotationSeq): BackendInstance[T]

    

    Definition Classes

    VerilatorExecutive → BackendExecutive

20. final def synchronized[T0](arg0: ⇒ T0): T0

    

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21. def toString(): String

    

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22. final def wait(): Unit

    

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    @throws( ... )

23. final def wait(arg0: Long, arg1: Int): Unit

    

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24. final def wait(arg0: Long): Unit

    

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