RemoveTempWires

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

def clone(): AnyRef

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def execute(state: CircuitState): CircuitState

Foreach Module in a firrtl circuit Find all the DefNodes with temp names and render their expression Remove all the found dev nodes recursively replace their references with their associated expression

final def getClass(): Class[_]

def hashCode(): Int

def inputForm: CircuitForm

final def isInstanceOf[T0]: Boolean

val logger: Logger

def name: String

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def outputForm: CircuitForm

final def runTransform(state: CircuitState): CircuitState

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def transform(state: CircuitState): CircuitState

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit

final def getMyAnnotations(state: CircuitState): Seq[Annotation]