Class

firrtl_interpreter.Memory

WritePort

Related Doc: package Memory

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case class WritePort(portName: String, latency: Int) extends MemoryPort with Product with Serializable

implements a write port with memory defined latency

portName

name of this writer

latency

the number of cycles between port and memory

Source
Memory.scala
Linear Supertypes
Serializable, Serializable, Product, Equals, MemoryPort, AnyRef, Any
Type Hierarchy
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Inherited
  1. WritePort
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. MemoryPort
  7. AnyRef
  8. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new WritePort(portName: String, latency: Int)

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    portName

    name of this writer

    latency

    the number of cycles between port and memory

Type Members

  1. case class WritePipeLineElement(enable: Boolean, address: Int, data: Concrete, mask: Concrete) extends Product with Serializable

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Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  4. var address: Int

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    Definition Classes
    MemoryPort

  5. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any

  6. var clock: Int

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    Definition Classes
    MemoryPort

  7. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  8. def cycle(): Unit

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  9. var data: Concrete

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    Definition Classes
    MemoryPort

  10. def elementFromSnapshot: WritePipeLineElement

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  11. var enable: Boolean

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    Definition Classes
    MemoryPort

  12. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  13. val fieldDependencies: Seq[String]

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    Definition Classes
    WritePort → MemoryPort

  14. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  15. val fullName: String

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    Definition Classes
    MemoryPort

  16. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any

  17. def getValue(fieldName: String): Concrete

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    Definition Classes
    WritePort → MemoryPort

  18. def inputHasChanged(): Unit

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  19. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any

  20. val latency: Int

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    the number of cycles between port and memory

    the number of cycles between port and memory

    Definition Classes
    WritePort → MemoryPort

  21. var mask: Concrete

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  22. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  23. final def notify(): Unit

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    Definition Classes
    AnyRef

  24. final def notifyAll(): Unit

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    Definition Classes
    AnyRef

  25. val outputFieldName: String

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    Definition Classes
    MemoryPort

  26. val pipeLine: ArrayBuffer[WritePipeLineElement]

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  27. val portName: String

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    name of this writer

    name of this writer

    Definition Classes
    WritePort → MemoryPort

  28. def setValue(fieldName: String, concreteValue: Concrete): Unit

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    Definition Classes
    WritePort → MemoryPort

  29. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef

  30. def toString(): String

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    Definition Classes
    WritePort → AnyRef → Any

  31. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  32. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  33. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from MemoryPort

Inherited from AnyRef

Inherited from Any

Ungrouped