CircuitState 1.1.1 - firrtl_interpreter.CircuitState

Instance Constructors

new CircuitState(inputPorts: Map[String, Concrete], outputPorts: Map[String, Concrete], registers: Map[String, Concrete], memories: Map[String, Memory], validNames: HashSet[String])

inputPorts
a map to current concrete value
outputPorts
a map to current concrete value
registers
a map to current concrete value

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def asInstanceOf[T0]: T0

Definition Classes
Any
var clockHigh: Boolean
def clone(): CircuitState

Clone this circuitState.
Clone this circuitState.
returns
a cloned version of this state

Definition Classes
CircuitState → AnyRef
Note
This does not yet clone memories. It merely copies them
def cycle(): Unit

prepare this cycle advance registers clear wire values cycle all memories
def cycleMemories(): Unit
def disableVCD(): Unit
val ephemera: HashMap[String, Concrete]
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getValue(key: String): Option[Concrete]
val inputPorts: Map[String, Concrete]

a map to current concrete value
def isEphemera(key: String): Boolean
def isInput(key: String): Boolean
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def isMemory(key: String): Boolean
def isOutput(key: String): Boolean
def isRegister(key: String): Boolean
var isStale: Boolean
def makeVCDLogger(dependencyGraph: DependencyGraph, circuitState: CircuitState, fileName: String = "out.firrtl_interpreter.vcd", showUnderscored: Boolean = false): Unit
val memories: Map[String, Memory]
var nameToConcreteValue: HashMap[String, Concrete]
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val nextRegisters: HashMap[String, Concrete]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val outputPorts: Map[String, Concrete]

a map to current concrete value
def prepareForDependencyResolution(): Unit

in order to compute dependencies, ephemera must be clear and their associated values cleared
def prettyString(dense: Boolean = true): String

prints a human readable version of the state,
prints a human readable version of the state,
dense
if true puts input, output and registers on one line each
val registers: Map[String, Concrete]

a map to current concrete value
val rhsOutputs: HashSet[String]
def setValue(key: String, concreteValue: Concrete, registerPoke: Boolean = false): Concrete
var stateCounter: Int
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
val validNames: HashSet[String]
var vcdLoggerOption: Option[VCD]
def vcdLowerClock(): Unit
var vcdOutputFileName: String
def vcdRaiseClock(): Unit
def vcdWireChangedwire(key: String, concrete: Concrete): Unit
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def writeVCD(): Unit

CircuitState

Related Docs: object CircuitState | package firrtl_interpreter

case class CircuitState(inputPorts: Map[String, Concrete], outputPorts: Map[String, Concrete], registers: Map[String, Concrete], memories: Map[String, Memory], validNames: HashSet[String]) extends Product with Serializable

Instance Constructors

new CircuitState(inputPorts: Map[String, Concrete], outputPorts: Map[String, Concrete], registers: Map[String, Concrete], memories: Map[String, Memory], validNames: HashSet[String])

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

var clockHigh: Boolean

def clone(): CircuitState

def cycle(): Unit

def cycleMemories(): Unit

def disableVCD(): Unit

val ephemera: HashMap[String, Concrete]

final def eq(arg0: AnyRef): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getValue(key: String): Option[Concrete]

val inputPorts: Map[String, Concrete]

def isEphemera(key: String): Boolean

def isInput(key: String): Boolean

final def isInstanceOf[T0]: Boolean

def isMemory(key: String): Boolean

def isOutput(key: String): Boolean

def isRegister(key: String): Boolean

var isStale: Boolean

def makeVCDLogger(dependencyGraph: DependencyGraph, circuitState: CircuitState, fileName: String = "out.firrtl_interpreter.vcd", showUnderscored: Boolean = false): Unit

val memories: Map[String, Memory]

var nameToConcreteValue: HashMap[String, Concrete]

final def ne(arg0: AnyRef): Boolean

val nextRegisters: HashMap[String, Concrete]

final def notify(): Unit

final def notifyAll(): Unit

val outputPorts: Map[String, Concrete]

def prepareForDependencyResolution(): Unit

def prettyString(dense: Boolean = true): String

val registers: Map[String, Concrete]

val rhsOutputs: HashSet[String]

def setValue(key: String, concreteValue: Concrete, registerPoke: Boolean = false): Concrete

var stateCounter: Int

final def synchronized[T0](arg0: ⇒ T0): T0

val validNames: HashSet[String]

var vcdLoggerOption: Option[VCD]

def vcdLowerClock(): Unit

var vcdOutputFileName: String

def vcdRaiseClock(): Unit

def vcdWireChangedwire(key: String, concrete: Concrete): Unit

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def writeVCD(): Unit

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from AnyRef

Inherited from Any

Ungrouped