Memory 1.2.1 - firrtl_interpreter.Memory

Instance Constructors

new Memory(info: Info, name: String, dataType: Type, depth: Int, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readWriters: Seq[String], readUnderWrite: String)

info
source level information
name
the name of this memory
dataType
type of each memory element
depth
number of elements
writeLatency
how many cycles before write happens
readLatency
how many cycles before read happens
readers
a list of named reader ports
writers
a list of named writer ports
readWriters
list of named read/write ports
readUnderWrite
behavior

Type Members

class DataStore extends AnyRef

wrap underlying data storage array so indexing is automatically constrained at depth
abstract class MemoryPort extends AnyRef
trait PipeLineElement extends AnyRef
case class ReadPort(portName: String, latency: Int) extends MemoryPort with Product with Serializable

implements a read port with memory defined latency
implements a read port with memory defined latency
portName
name of this reader
latency
the number of cycles between port and memory
case class ReadWritePort(portName: String) extends MemoryPort with Product with Serializable
case class WritePort(portName: String, latency: Int) extends MemoryPort with Product with Serializable

implements a write port with memory defined latency
implements a write port with memory defined latency
portName
name of this writer
latency
the number of cycles between port and memory

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
val addressWidth: Int
final def asInstanceOf[T0]: T0

Definition Classes
Any
val bigDepth: BigInt
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
def cycle(): Unit

used to inform this memory that a cycle has passed
val dataStore: DataStore
val dataType: Type

type of each memory element
val dataWidth: Int
val depth: Int

number of elements
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def forceWrite(offset: Int, value: BigInt): Unit
def getAllFieldDependencies: Seq[String]
def getAllOutputFields: Seq[(String, Seq[String])]
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getValue(key: String): Concrete
def hashCode(): Int

Definition Classes
AnyRef → Any
val info: Info

source level information
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def log(msg: ⇒ String): Unit

Definition Classes
SimpleLogger
val maxMemoryInDefaultDisplay: Int
var moduloIndex: Boolean
val name: String

the name of this memory
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val ports: Map[String, MemoryPort]
val readLatency: Int

how many cycles before read happens
val readPorts: Array[ReadPort]
val readUnderWrite: String

behavior
val readWritePorts: Array[ReadWritePort]
val readWriters: Seq[String]

list of named read/write ports
val readers: Seq[String]

a list of named reader ports
def setValue(key: String, concreteValue: Concrete): Unit

delegate the concrete value to a port various actions may ensue depending on the
delegate the concrete value to a port various actions may ensue depending on the
key
full ram.port.field specifier
concreteValue
current value
def setVerbose(value: Boolean = true): Unit

Definition Classes
SimpleLogger
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
Memory → AnyRef → Any
var verbose: Boolean

Definition Classes
SimpleLogger
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
val writeLatency: Int

how many cycles before write happens
val writePorts: Array[WritePort]
val writers: Seq[String]

a list of named writer ports

Memory

Related Docs: object Memory | package firrtl_interpreter

class Memory extends SimpleLogger

Instance Constructors

new Memory(info: Info, name: String, dataType: Type, depth: Int, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readWriters: Seq[String], readUnderWrite: String)

Type Members

class DataStore extends AnyRef

abstract class MemoryPort extends AnyRef

trait PipeLineElement extends AnyRef

case class ReadPort(portName: String, latency: Int) extends MemoryPort with Product with Serializable

case class ReadWritePort(portName: String) extends MemoryPort with Product with Serializable

case class WritePort(portName: String, latency: Int) extends MemoryPort with Product with Serializable

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

val addressWidth: Int

final def asInstanceOf[T0]: T0

val bigDepth: BigInt

def clone(): AnyRef

def cycle(): Unit

val dataStore: DataStore

val dataType: Type

val dataWidth: Int

val depth: Int

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

def forceWrite(offset: Int, value: BigInt): Unit

def getAllFieldDependencies: Seq[String]

def getAllOutputFields: Seq[(String, Seq[String])]

final def getClass(): Class[_]

def getValue(key: String): Concrete

def hashCode(): Int

val info: Info

final def isInstanceOf[T0]: Boolean

def log(msg: ⇒ String): Unit

val maxMemoryInDefaultDisplay: Int

var moduloIndex: Boolean

val name: String

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

val ports: Map[String, MemoryPort]

val readLatency: Int

val readPorts: Array[ReadPort]

val readUnderWrite: String

val readWritePorts: Array[ReadWritePort]

val readWriters: Seq[String]

val readers: Seq[String]

def setValue(key: String, concreteValue: Concrete): Unit

def setVerbose(value: Boolean = true): Unit

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

var verbose: Boolean

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

val writeLatency: Int

val writePorts: Array[WritePort]

val writers: Seq[String]

Inherited from SimpleLogger

Inherited from AnyRef

Inherited from Any

Ungrouped