Class

firrtl.ir

ExtModule

Related Doc: package ir

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case class ExtModule(info: Info, name: String, ports: Seq[Port], defname: String, params: Seq[Param]) extends DefModule with Product with Serializable

External Module

Generally used for Verilog black boxes

defname

Defined name of the external module (ie. the name Firrtl will emit)

Linear Supertypes
Serializable, Serializable, Product, Equals, DefModule, IsDeclaration, HasInfo, HasName, FirrtlNode, AnyRef, Any
Type Hierarchy Learn more about scaladoc diagrams
Ordering
  1. Alphabetic
  2. By inheritance
Inherited
  1. ExtModule
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. DefModule
  7. IsDeclaration
  8. HasInfo
  9. HasName
  10. FirrtlNode
  11. AnyRef
  12. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new ExtModule(info: Info, name: String, ports: Seq[Port], defname: String, params: Seq[Param])

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    defname

    Defined name of the external module (ie. the name Firrtl will emit)

Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  4. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any

  5. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  6. val defname: String

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    Defined name of the external module (ie.

    Defined name of the external module (ie. the name Firrtl will emit)

  7. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  8. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  9. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any

  10. val info: Info

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    Definition Classes
    ExtModule → DefModule → HasInfo

  11. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any

  12. def mapPort(f: (Port) ⇒ Port): DefModule

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    Definition Classes
    ExtModule → DefModule

  13. def mapStmt(f: (Statement) ⇒ Statement): DefModule

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    Definition Classes
    ExtModule → DefModule

  14. def mapString(f: (String) ⇒ String): DefModule

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    Definition Classes
    ExtModule → DefModule

  15. val name: String

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    Definition Classes
    ExtModule → DefModule → HasName

  16. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  17. final def notify(): Unit

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    Definition Classes
    AnyRef

  18. final def notifyAll(): Unit

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    Definition Classes
    AnyRef

  19. val params: Seq[Param]

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  20. val ports: Seq[Port]

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    Definition Classes
    ExtModule → DefModule

  21. def serialize: String

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    Definition Classes
    ExtModule → FirrtlNode

  22. def serializeHeader(tpe: String): String

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    Attributes
    protected
    Definition Classes
    DefModule

  23. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef

  24. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  25. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  26. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from DefModule

Inherited from IsDeclaration

Inherited from HasInfo

Inherited from HasName

Inherited from FirrtlNode

Inherited from AnyRef

Inherited from Any

Ungrouped