BackendCompilationUtilities

Value Members

1. final def !=(arg0: Any): Boolean

   

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2. final def ##(): Int

   

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3. final def ==(arg0: Any): Boolean

   

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4. lazy val TestDirectory: File

   

   Parent directory for tests

5. final def asInstanceOf[T0]: T0

   

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6. def clone(): AnyRef

   

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   protected[java.lang]

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7. def copyResourceToFile(name: String, file: File): Unit

   

   Copy the contents of a resource to a destination file.

8. def cppToExe(prefix: String, dir: File): ProcessBuilder

   

9. def createTestDirectory(testName: String): File

   

   Create a test directory

   Create a test directory

   Will create outer directory called testName then inner directory based on the current time

10. final def eq(arg0: AnyRef): Boolean

    

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11. def equals(arg0: Any): Boolean

    

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12. def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String = ""): Boolean

    

13. def executeExpectingSuccess(prefix: String, dir: File): Boolean

    

14. def finalize(): Unit

    

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15. def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder

    

    compule chirrtl to verilog by using a separate process

    compule chirrtl to verilog by using a separate process

    prefix

    basename of the file

    dir

    directory where file lives

    returns

    true if compiler completed successfully

16. final def getClass(): Class[_]

    

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17. def hashCode(): Int

    

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18. final def isInstanceOf[T0]: Boolean

    

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19. def makeHarness(template: (String) ⇒ String, post: String)(f: File): File

    

20. final def ne(arg0: AnyRef): Boolean

    

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21. final def notify(): Unit

    

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22. final def notifyAll(): Unit

    

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23. final def synchronized[T0](arg0: ⇒ T0): T0

    

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24. def timeStamp: String

    

25. def toString(): String

    

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26. def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File): ProcessBuilder

    

    Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.

    Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.

    The Verilator prefix will be V$dutFile, and running this will generate C++ sources and headers as well as a makefile to compile them.

    Verilator will automatically locate the top-level module as the one among all the files which are not included elsewhere. If multiple ones exist, the compilation will fail.

    dutFile

    name of the DUT .v without the .v extension

    dir

    output directory

    vSources

    list of additional Verilog sources to compile

    cppHarness

    C++ testharness to compile/link against

27. final def wait(): Unit

    

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28. final def wait(arg0: Long, arg1: Int): Unit

    

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29. final def wait(arg0: Long): Unit

    

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