VerilogEmitter

Value Members

1. final def !=(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

2. final def ##(): Int

   

   Definition Classes

   AnyRef → Any

3. final def ==(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

4. def AND(e1: WrappedExpression, e2: WrappedExpression): Expression

   

5. final def asInstanceOf[T0]: T0

   

   Definition Classes

   Any

6. def clone(): AnyRef

   

   Attributes

   protected[java.lang]

   Definition Classes

   AnyRef

   Annotations

   @throws( ... )

7. def emit(state: CircuitState, writer: Writer): Unit

   

   Definition Classes

   VerilogEmitter → Emitter

8. def emit(x: Any, top: Int)(implicit w: Writer): Unit

   

9. def emit(x: Any)(implicit w: Writer): Unit

   

10. def emit_verilog(m: Module, moduleMap: Map[String, DefModule])(implicit w: Writer): DefModule

    

11. final def eq(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

12. def equals(arg0: Any): Boolean

    

    Definition Classes

    AnyRef → Any

13. def execute(state: CircuitState): CircuitState

    

    Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

    Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

    state

    Input Firrtl AST

    returns

    A transformed Firrtl AST

    Definition Classes

    VerilogEmitter → SeqTransform → Transform

14. def finalize(): Unit

    

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

15. final def getClass(): Class[_]

    

    Definition Classes

    AnyRef → Any

16. final def getMyAnnotations(state: CircuitState): Seq[Annotation]

    

    Convenience method to get annotations relevant to this Transform

    Convenience method to get annotations relevant to this Transform

    state

    The CircuitState form which to extract annotations

    returns

    A collection of annotations

    Definition Classes

    Transform

17. def hashCode(): Int

    

    Definition Classes

    AnyRef → Any

18. def inputForm: LowForm.type

    

    The firrtl.CircuitForm that this transform requires to operate on

    The firrtl.CircuitForm that this transform requires to operate on

    Definition Classes

    VerilogEmitter → Transform

19. final def isInstanceOf[T0]: Boolean

    

    Definition Classes

    Any

20. val logger: Logger

    

    Definition Classes

    LazyLogging

21. def name: String

    

    A convenience function useful for debugging and error messages

    A convenience function useful for debugging and error messages

    Definition Classes

    Transform

22. final def ne(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

23. final def notify(): Unit

    

    Definition Classes

    AnyRef

24. final def notifyAll(): Unit

    

    Definition Classes

    AnyRef

25. def op_stream(doprim: DoPrim): Seq[Any]

    

26. def outputForm: LowForm.type

    

    The firrtl.CircuitForm that this transform outputs

    The firrtl.CircuitForm that this transform outputs

    Definition Classes

    VerilogEmitter → Transform

27. def preamble: String

    

    Preamble for every emitted Verilog file

28. def remove_root(ex: Expression): Expression

    

29. final def runTransform(state: CircuitState): CircuitState

    

    Perform the transform and update annotations.

    Perform the transform and update annotations.

    state

    Input Firrtl AST

    returns

    A transformed Firrtl AST

    Definition Classes

    Transform

30. def runTransforms(state: CircuitState): CircuitState

    

    Attributes

    protected

    Definition Classes

    SeqTransformBased

31. def stringify(tpe: GroundType): String

    

32. def stringify(param: Param): String

    

    Turn Params into Verilog Strings

33. final def synchronized[T0](arg0: ⇒ T0): T0

    

    Definition Classes

    AnyRef

34. val tab: String

    

35. def toString(): String

    

    Definition Classes

    AnyRef → Any

36. def transforms: Seq[Pass]

    

    Definition Classes

    VerilogEmitter → SeqTransformBased

37. def v_print(e: Expression)(implicit w: Writer): Unit

    

38. final def wait(): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

39. final def wait(arg0: Long, arg1: Int): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

40. final def wait(arg0: Long): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

41. def wref(n: String, t: Type): WRef