MALE
firrtl
MAX
PrimOps
MIN
PrimOps
MINUS
PrimOps
MInfer
firrtl
MPort
passes
MPortDir
firrtl
MPortDirMap
CInferMDir
MPortMap
RemoveCHIRRTL
MPortTypeMap
RemoveCHIRRTL
MPorts
passes
MRead
firrtl
MReadWrite
firrtl
MSet
GroupComponents
MWrite
firrtl
Mappers
firrtl
MaxWidth
firrtl CheckWidths
MemDataTypeMap
LowerTypes
MemKind
firrtl
MemPortMap
MemPortUtils
MemPortUtils
passes
MemTransformUtils
memlib
MemWithFlipException
CheckChirrtl CheckHighForm
MemoizedHash
firrtl
Memories
MemPortUtils
MidForm
firrtl
MiddleFirrtlCompiler
firrtl
MiddleFirrtlEmitter
firrtl
MiddleFirrtlToLowFirrtl
firrtl
MinWidth
firrtl
MinimumLowFirrtlOptimization
firrtl
MinimumVerilogCompiler
firrtl
MinusWidth
firrtl
Modifications
wiring
Module
ir
ModuleGraph
firrtl
ModuleMap
Mappers
ModuleName
annotations
ModuleNameSerializer
JsonProtocol
ModuleNamespaceAnnotation
analyses
ModuleNotDefinedException
CheckChirrtl CheckHighForm
Modules
MemPortUtils
Mul
PrimOps
MultiInfo
ir
MutableDiGraph
graph
Mux
ir
MuxClock
CheckTypes
MuxCondUInt
CheckTypes
MuxPassiveTypes
CheckTypes
MuxSameType
CheckTypes
main
Driver Circuit
makeDirectory
FileUtils
makeHarness
BackendCompilationUtilities
makeScope
Logger
makeTargetDir
ExecutionOptionsManager
male
DataRef
map
CircuitMap ExprMap ModuleMap StmtMap TypeMap WidthMap Lineage
mapExpr
CDefMPort CDefMemory EmptyExpression VRandom WDefInstance WDefInstanceConnector WInvalid WRef WSubAccess WSubField WSubIndex WVoid Attach Block Conditionally Connect DefInstance DefMemory DefNode DefRegister DefWire DoPrim EmptyStmt Expression FixedLiteral IsInvalid Mux PartialConnect Print Reference SIntLiteral Statement Stop SubAccess SubField SubIndex UIntLiteral ValidIf DefAnnotatedMemory
mapInfo
CDefMPort CDefMemory WDefInstance WDefInstanceConnector Attach Block Circuit Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire EmptyStmt ExtModule IsInvalid Module PartialConnect Print Statement Stop DefAnnotatedMemory
mapModule
Circuit
mapPort
DefModule ExtModule Module
mapStmt
CDefMPort CDefMemory WDefInstance WDefInstanceConnector Attach Block Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire EmptyStmt ExtModule IsInvalid Module PartialConnect Print Statement Stop DefAnnotatedMemory
mapString
CDefMPort CDefMemory WDefInstance WDefInstanceConnector Attach Block Circuit Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire EmptyStmt ExtModule IsInvalid Module PartialConnect Print Statement Stop DefAnnotatedMemory
mapType
CDefMPort CDefMemory EmptyExpression VRandom WDefInstance WDefInstanceConnector WInvalid WRef WSubAccess WSubField WSubIndex WVoid Attach Block BundleType Conditionally Connect DefInstance DefMemory DefNode DefRegister DefWire DoPrim EmptyStmt Expression FixedLiteral GroundType IsInvalid Mux PartialConnect Print Reference SIntLiteral Statement Stop SubAccess SubField SubIndex Type UIntLiteral UnknownType ValidIf VectorType DefAnnotatedMemory
mapWidth
EmptyExpression ExpWidth MaxWidth MinWidth MinusWidth PlusWidth VRandom VarWidth WInvalid WRef WSubAccess WSubField WSubIndex WVoid AggregateType AnalogType ClockType DoPrim Expression FixedLiteral FixedType Mux Reference SIntLiteral SIntType SubAccess SubField SubIndex Type UIntLiteral UIntType UnknownType ValidIf
mask
DataRef
maskBits
ReplaceMemMacros
maskGran
DefAnnotatedMemory
max
Utils Width
mdir
FIRRTLParser
mem
CDefMPort
memDelayMod
VerilogMemDelays
memDelayStmt
VerilogMemDelays
memField
FIRRTLParser
memPortField
MemPortUtils MemTransformUtils
memRef
DefAnnotatedMemory
memToBundle
ReplaceMemMacros
memToFlattenBundle
ReplaceMemMacros
memType
MemPortUtils
memlib
passes
mergeRef
Utils
mergeTransforms
CompilerUtils
message
EmitterException FirrtlExecutionFailure InvalidEscapeCharException InvalidStringLitException ParameterNotSpecifiedException ParameterRedefinedException SyntaxErrorsException AnnotationException
min
Utils Width
module
WDefInstance WDefInstanceConnector DefInstanceGraphNode ComponentName FIRRTLParser DefInstance Source
moduleBlock
FIRRTLParser
moduleMap
InstanceGraph
moduleOrder
InstanceGraph
module_type
Utils
modules
Circuit
msg
OptionsException DeclarationNotFoundException InvalidAnnotationJSONException WiringException
mux_type
Utils
mux_type_and_widths
Utils