OfModule
InstanceKey
TargetToken
fromDefInstanceToTargetToken
fromDefModuleToTargetToken
fromStringToTargetToken
fromWDefInstanceToTargetToken
Old
ReadUnderWrite
OneFilePerModule
firrtl
OpNoMixFix
CheckTypes
OpNotAllSameType
CheckTypes
OpNotAllUInt
CheckTypes
OpNotAnalog
CheckTypes
OpNotCorrectType
CheckTypes
OpNotGround
CheckTypes
OpNotUInt
CheckTypes
Open
ir
OptimizableExtModuleAnnotation
transforms
OptionsException
Driver
options
OptionsHelpException
options
OptionsView
options
Or
PrimOps
Orientation
ir
Orr
PrimOps
Output
ir
OutputAnnotationFileAnnotation
options
OutputCaptor
Logger
OutputConfig
firrtl
OutputConfigFileName
memlib
OutputFileAnnotation
stage
o1
PrimOps
o2
PrimOps
o3
PrimOps
ofModule
InstanceTarget
ofModuleTarget
InstanceTarget
onExpr
InlineBitExtractionsTransform
InlineCastsTransform
LegalizeAndReductionsTransform
ReplaceTruncatingArithmetic
onMod
CombineCats
InlineBitExtractionsTransform
InlineCastsTransform
LegalizeAndReductionsTransform
LegalizeClocksTransform
ReplaceTruncatingArithmetic
onModule
AddDescriptionNodes
RemoveAllButClocks
SimplifyMems
onStmt
AddDescriptionNodes
RemoveAllButClocks
CombineCats
InlineBitExtractionsTransform
InlineCastsTransform
LegalizeAndReductionsTransform
LegalizeClocksTransform
RenameModules
ReplaceTruncatingArithmetic
one
Utils
op
IsAdd
IsMax
IsMin
IsMul
MultiAry
DoPrim
op_stream
VerilogEmitter
optAdd
GenericTarget
optimize
ConstantPropagation
optionalPrerequisiteOf
AddDescriptionNodes
DependencyAPIMigration
Transform
VerilogEmitter
GetNamespace
EliminateTargetPaths
CheckResets
DependencyAPI
DependencyManager
AddDefaults
Checks
ConvertLegacyAnnotations
DeletedWrapper
GetIncludes
WriteOutputAnnotations
CheckChirrtl
CheckFlows
CheckHighForm
CheckTypes
CheckWidths
CommonSubexpressionElimination
InferBinaryPoints
InlineInstances
Legalize
LowerTypes
PadWidths
RemoveEmpty
RemoveValidIf
SplitExpressions
TrimIntervals
VerilogModulusCleanup
VerilogPrep
ClockListTransform
CreateMemoryAnnotations
InferReadWrite
ReplSeqMem
ReplaceMemMacros
ResolveMemoryReference
VerilogMemDelays
WiringTransform
FirrtlStage
AddCircuit
AddDefaults
AddImplicitEmitter
AddImplicitOutputFile
CatchExceptions
Checks
Compiler
AddImplicitAnnotationFile
AddImplicitEmitter
AddImplicitFirrtlFile
AddImplicitOutputFile
WriteEmitted
WrappedTransform
BlackBoxSourceHelper
CheckCombLoops
CombineCats
ConstantPropagation
DeadCodeElimination
DedupModules
FixAddingNegativeLiterals
Flatten
FlattenRegUpdate
GroupComponents
InlineBitExtractionsTransform
InlineCastsTransform
LegalizeAndReductionsTransform
LegalizeClocksTransform
PropagatePresetAnnotations
RemoveReset
RemoveWires
RenameModules
ReplaceTruncatingArithmetic
SimplifyMems
TopWiringTransform
VerilogRename
Checks
optionalPrerequisites
AddDescriptionNodes
DependencyAPIMigration
Transform
GetNamespace
EliminateTargetPaths
CheckResets
DependencyAPI
DependencyManager
InlineInstances
Legalize
PadWidths
RemoveEmpty
VerilogModulusCleanup
VerilogPrep
ClockListTransform
CreateMemoryAnnotations
InferReadWrite
ReplSeqMem
ReplaceMemMacros
ResolveMemoryReference
WiringTransform
FirrtlStage
BlackBoxSourceHelper
CheckCombLoops
CombineCats
ConstantPropagation
DeadCodeElimination
FixAddingNegativeLiterals
Flatten
FlattenRegUpdate
GroupComponents
InlineBitExtractionsTransform
InlineCastsTransform
LegalizeAndReductionsTransform
LegalizeClocksTransform
PropagatePresetAnnotations
RemoveReset
RemoveWires
RenameModules
ReplaceTruncatingArithmetic
SimplifyMems
TopWiringTransform
VerilogRename
options
EmitAllModulesAnnotation
EmitCircuitAnnotation
firrtl
HasShellOptions
InputAnnotationFileAnnotation
OutputAnnotationFileAnnotation
TargetDirAnnotation
WriteDeletedAnnotation
InlineInstances
ClockListTransform
InferReadWrite
MemLibOptions
ReplSeqMem
CompilerAnnotation
FirrtlFileAnnotation
FirrtlSourceAnnotation
InfoModeAnnotation
OutputFileAnnotation
RunFirrtlTransformAnnotation
CheckCombLoops
DeadCodeElimination
NoCircuitDedupAnnotation
ClassLogLevelAnnotation
LogClassNamesAnnotation
LogFileAnnotation
LogLevelAnnotation
originalMemoryNameOpt
LoadMemoryAnnotation
others
IsAdd
IsMax
IsMin
IsMul
outputAnnotationFileName
FirrtlExecutionOptions
outputBuffer
ConfWriter
YamlFileWriter
outputConfig
ClockListAnnotation
ReplSeqMemAnnotation
outputFileName
FirrtlOptions
outputFileNameOverride
FirrtlExecutionOptions
outputForm
ChirrtlToHighFirrtl
DependencyAPIMigration
FirrtlEmitter
HighFirrtlToMiddleFirrtl
IRToWorkingIR
LowFirrtlOptimization
MiddleFirrtlToLowFirrtl
MinimumLowFirrtlOptimization
ResolveAndCheck
Transform
VerilogEmitter
SimpleTransform
WrappedTransform
IdentityTransform
AnalyzeCircuit
AnalyzeCircuit
outputFunction
TopWiringOutputFilesAnnotation
outputSuffix
ChirrtlForm
CircuitForm
EmittedComponent
EmittedFirrtlCircuit
EmittedFirrtlModule
EmittedVerilogCircuit
EmittedVerilogModule
Emitter
FirrtlEmitter
FirrtlExecutionOptions
HighForm
LowForm
MidForm
SystemVerilogEmitter
UnknownForm
VerilogEmitter
GroupAnnotation