Base type of auxiliary information
Target pointing to a FIRRTL firrtl.ir.Circuit
Target pointing to a FIRRTL firrtl.ir.Circuit
Name of a FIRRTL circuit
Concretely points to a FIRRTL target, no generic selectors IsLegal
Represents incomplete or non-standard Targets
Represents incomplete or non-standard Targets
Optional circuit name
Optional module name
TargetTokens to represent the target in a circuit and module
Points to an instance declaration of a module (termed an ofModule)
Points to an instance declaration of a module (termed an ofModule)
Encapsulating circuit
Root module (e.g. the base module of this target)
Path through instance/ofModules
Name of the instance
Name of the instance's module
A component of a FIRRTL Module (e.g.
A component of a FIRRTL Module (e.g. cannot point to a CircuitTarget or ModuleTarget)
A member of a FIRRTL Circuit (e.g.
A member of a FIRRTL Circuit (e.g. cannot point to a CircuitTarget) Concrete Subclasses are: ModuleTarget, InstanceTarget, and ReferenceTarget
References a module-like target (e.g.
References a module-like target (e.g. a ModuleTarget or an InstanceTarget)
Firrtl implementation for load memory
Firrtl implementation for load memory
memory to load
name of input file
use $readmemh
or $readmemb
Initialize the target
memory with the array of values
which must be the same size as the memory depth.
Represents the initial value of the annotated memory.
Represents the initial value of the annotated memory. While not supported on normal ASIC flows, it can be useful for simulation and FPGA flows. This annotation is consumed by the verilog emitter.
Representation of the two types of readmem
statements available in Verilog.
Randomly initialize the target
memory.
Randomly initialize the target
memory. This is the same as the default behavior.
Initialize all entries of the target
memory with the scalar value
.
Target pointing to a FIRRTL firrtl.ir.DefModule
Target pointing to a FIRRTL firrtl.ir.DefModule
Circuit containing the module
Name of the module
MultiTargetAnnotation keeps the renamed targets grouped within a single annotation.
Named classes associate an annotation with a component in a Firrtl circuit
If an Annotation does not target any Named thing in the circuit, then all updates just return the Annotation itself
Transform all registers connected to the targeted AsyncReset tree into bitstream preset registers Impacts all registers connected to any child (cross module) of the target AsyncReset
Transform all registers connected to the targeted AsyncReset tree into bitstream preset registers Impacts all registers connected to any child (cross module) of the target AsyncReset
ReferenceTarget to an AsyncReset
Target pointing to a declared named component in a firrtl.ir.DefModule This includes: firrtl.ir.Port, firrtl.ir.DefWire, firrtl.ir.DefRegister, firrtl.ir.DefInstance, firrtl.ir.DefMemory, firrtl.ir.DefNode
Target pointing to a declared named component in a firrtl.ir.DefModule This includes: firrtl.ir.Port, firrtl.ir.DefWire, firrtl.ir.DefRegister, firrtl.ir.DefInstance, firrtl.ir.DefMemory, firrtl.ir.DefNode
Name of the encapsulating circuit
Name of the root module of this reference
Path through instance/ofModules
Name of component
Subcomponent of this reference, e.g. field or index
An Annotation that targets a single Named thing
Refers to something in a FIRRTL firrtl.ir.Circuit.
Refers to something in a FIRRTL firrtl.ir.Circuit. Used for Annotation targets.
Can be in various states of completion/resolved:
Building block to represent a Target of a FIRRTL component
Object containing all TargetToken subclasses